path: root/include/llvm/CodeGen/MachineInstr.h

//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
//
// This file contains the declaration of the MachineInstr class, which is the
// basic representation for all target dependant machine instructions used by
// the back end.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_CODEGEN_MACHINEINSTR_H
#define LLVM_CODEGEN_MACHINEINSTR_H

#include "llvm/Annotation.h"
#include "Support/iterator"
#include "Support/NonCopyable.h"
#include <vector>
class Value;
class Function;
class MachineBasicBlock;
class TargetMachine;

typedef int MachineOpCode;

/// MOTy - MachineOperandType - This namespace contains an enum that describes
/// how the machine operand is used by the instruction: is it read, defined, or
/// both?  Note that the MachineInstr/Operator class currently uses bool
/// arguments to represent this information instead of an enum.  Eventually this
/// should change over to use this _easier to read_ representation instead.
///
namespace MOTy {
  enum UseType {
    Use,             /// This machine operand is only read by the instruction
    Def,             /// This machine operand is only written by the instruction
    UseAndDef        /// This machine operand is read AND written
  };
}

//---------------------------------------------------------------------------
// class MachineOperand 
// 
// Purpose:
//   Representation of each machine instruction operand.
//   This class is designed so that you can allocate a vector of operands
//   first and initialize each one later.
//
//   E.g, for this VM instruction:
//		ptr = alloca type, numElements
//   we generate 2 machine instructions on the SPARC:
// 
//		mul Constant, Numelements -> Reg
//		add %sp, Reg -> Ptr
// 
//   Each instruction has 3 operands, listed above.  Of those:
//   -	Reg, NumElements, and Ptr are of operand type MO_Register.
//   -	Constant is of operand type MO_SignExtendedImmed on the SPARC.
//	
//   For the register operands, the virtual register type is as follows:
//	
//   -  Reg will be of virtual register type MO_MInstrVirtualReg.  The field
//	MachineInstr* minstr will point to the instruction that computes reg.
// 
//   -	%sp will be of virtual register type MO_MachineReg.
//	The field regNum identifies the machine register.
// 
//   -	NumElements will be of virtual register type MO_VirtualReg.
//	The field Value* value identifies the value.
// 
//   -	Ptr will also be of virtual register type MO_VirtualReg.
//	Again, the field Value* value identifies the value.
// 
//---------------------------------------------------------------------------

class MachineOperand {
public:
  enum MachineOperandType {
    MO_VirtualRegister,		// virtual register for *value
    MO_MachineRegister,		// pre-assigned machine register `regNum'
    MO_CCRegister,
    MO_SignExtendedImmed,
    MO_UnextendedImmed,
    MO_PCRelativeDisp,
  };
  
private:
  // Bit fields of the flags variable used for different operand properties
  static const char DEFFLAG    = 0x1;  // this is a def of the operand
  static const char DEFUSEFLAG = 0x2;  // this is both a def and a use
  static const char HIFLAG32   = 0x4;  // operand is %hi32(value_or_immedVal)
  static const char LOFLAG32   = 0x8;  // operand is %lo32(value_or_immedVal)
  static const char HIFLAG64   = 0x10; // operand is %hi64(value_or_immedVal)
  static const char LOFLAG64   = 0x20; // operand is %lo64(value_or_immedVal)
  
private:
  union {
    Value*	value;		// BasicBlockVal for a label operand.
				// ConstantVal for a non-address immediate.
				// Virtual register for an SSA operand,
				// including hidden operands required for
				// the generated machine code.     
    int64_t immedVal;		// constant value for an explicit constant
  };

  MachineOperandType opType:8;  // Pack into 8 bits efficiently after flags.
  char flags;                   // see bit field definitions above
  int regNum;	                // register number for an explicit register
                                // will be set for a value after reg allocation
private:
  MachineOperand()
    : immedVal(0),
      opType(MO_VirtualRegister),
      flags(0),
      regNum(-1) {}

  MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
    : immedVal(ImmVal),
      opType(OpTy),
      flags(0),
      regNum(-1) {}

  MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
    : immedVal(0),
      opType(OpTy),
      regNum(Reg) {
    switch (UseTy) {
    case MOTy::Use:       flags = 0; break;
    case MOTy::Def:       flags = DEFFLAG; break;
    case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
    default: assert(0 && "Invalid value for UseTy!");
    }
  }

  MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy) 
    : value(V), opType(OpTy), regNum(-1) {
    switch (UseTy) {
    case MOTy::Use:       flags = 0; break;
    case MOTy::Def:       flags = DEFFLAG; break;
    case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
    default: assert(0 && "Invalid value for UseTy!");
    }
  }

public:
  MachineOperand(const MachineOperand &M)
    : immedVal(M.immedVal),
      opType(M.opType),
      flags(M.flags),
      regNum(M.regNum) {}

  ~MachineOperand() {}
  
  // Accessor methods.  Caller is responsible for checking the
  // operand type before invoking the corresponding accessor.
  // 
  MachineOperandType getType() const { return opType; }

  inline Value*		getVRegValue	() const {
    assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 
	   opType == MO_PCRelativeDisp);
    return value;
  }
  inline Value*		getVRegValueOrNull() const {
    return (opType == MO_VirtualRegister || opType == MO_CCRegister || 
            opType == MO_PCRelativeDisp)? value : NULL;
  }
  inline int            getMachineRegNum() const {
    assert(opType == MO_MachineRegister);
    return regNum;
  }
  inline int64_t	getImmedValue	() const {
    assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
    return immedVal;
  }
  bool		opIsDef		() const { return flags & DEFFLAG; }
  bool		opIsDefAndUse	() const { return flags & DEFUSEFLAG; }
  bool          opHiBits32      () const { return flags & HIFLAG32; }
  bool          opLoBits32      () const { return flags & LOFLAG32; }
  bool          opHiBits64      () const { return flags & HIFLAG64; }
  bool          opLoBits64      () const { return flags & LOFLAG64; }

  // used to check if a machine register has been allocated to this operand
  inline bool   hasAllocatedReg() const {
    return (regNum >= 0 &&
            (opType == MO_VirtualRegister || opType == MO_CCRegister || 
             opType == MO_MachineRegister));
  }

  // used to get the reg number if when one is allocated
  inline int  getAllocatedRegNum() const {
    assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 
	   opType == MO_MachineRegister);
    return regNum;
  }

  
  friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);

private:

  // Construction methods needed for fine-grain control.
  // These must be accessed via coresponding methods in MachineInstr.
  void markDef()       { flags |= DEFFLAG; }
  void markDefAndUse() { flags |= DEFUSEFLAG; }
  void markHi32()      { flags |= HIFLAG32; }
  void markLo32()      { flags |= LOFLAG32; }
  void markHi64()      { flags |= HIFLAG64; }
  void markLo64()      { flags |= LOFLAG64; }
  
  // Replaces the Value with its corresponding physical register after
  // register allocation is complete
  void setRegForValue(int reg) {
    assert(opType == MO_VirtualRegister || opType == MO_CCRegister || 
	   opType == MO_MachineRegister);
    regNum = reg;
  }
  
  friend class MachineInstr;</