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path: root/utils/TableGen/CodeGenTarget.cpp
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2009-08-11Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson
while the latter is capable of representing either a primitive or an extended type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11Fix a few more places in TableGen that need to handle EVT::vAny types.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78643 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11Add a new overloaded EVT::vAny type for use in TableGen to allow intrinsicBob Wilson
arguments that are vectors of any size and element type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78631 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson
own struct type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-29Match X86 register names to number.Daniel Dunbar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77404 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-15Remove the v3i32 and v3f32 value types: they are notDuncan Sands
native for any supported targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75785 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-14Revert 75308.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75565 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10Add new vector types for 192-bit, 348-bit and 512-bit sizes.Bob Wilson
These are needed to represent ARM Neon struct datatypes containing 2, 3 or 4 separate vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75308 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-10Refactor TableGen's llvm::getName to share code with llvm::getEnumName,Bob Wilson
since names are the same for almost all the types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75302 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-06Add new ValueType for metadata.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74882 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-03Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar
- Sorry, I can't help myself. - No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-29Add more vector ValueTypes for AVX and other extended vector instructionDavid Greene
sets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74427 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02Revert 72707 and 72709, for the moment.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01Make the implicit inputs and outputs of target-independentDale Johannesen
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to) instead of MVT::Flag. Remove CARRY_FALSE in favor of 0; adjust all target-independent code to use this format. Most targets will still produce a Flag-setting target-dependent version when selection is done. X86 is converted to use i32 instead, which means TableGen needs to produce different code in xxxGenDAGISel.inc. This keys off the new supportsHasI1 bit in xxxInstrInfo, currently set only for X86; in principle this is temporary and should go away when all other targets have been converted. All relevant X86 instruction patterns are modified to represent setting and using EFLAGS explicitly. The same can be done on other targets. The immediate behavior change is that an ADC/ADD pair are no longer tightly coupled in the X86 scheduler; they can be separated by instructions that don't clobber the flags (MOV). I will soon add some peephole optimizations based on using other instructions that set the flags to feed into ADC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-16Fix PR3994: LLVMMatchType arguments do not refer to absolute return valueBob Wilson
and argument positions but only to the overloaded intrinsic parameters. Keep a separate list of these overloaded parameters in CodeGenTarget.cpp so they can be resolved easily. Remove assertions from IntrinsicEmitter.cpp: they were harmless but confusing, and the assertions elsewhere in TableGen will catch any incorrect values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69316 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman
it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-13Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman
This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-05Reapply 63765. Patches for clang and llvm-gcc to follow.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63812 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04Reverting 63765. This broke the build of both clangDale Johannesen
and llvm-gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63786 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-04New feature: add support for target intrinsics being defined in theNate Begeman
target directories themselves. This also means that VMCore no longer needs to know about every target's list of intrinsics. Future work will include converting the PowerPC target to this interface as an example implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63765 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-12add nocapture attribute to llvm.mem* intrinsics and have tblgenChris Lattner
parse them. tblgen doesn't yet do anything with this info though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62065 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-07Improve support for type-generic vector intrinsics by teaching TableGen howBob Wilson
to handle LLVMMatchType intrinsic parameters, and by adding new subclasses of LLVMMatchType to match vector types with integral elements that are either twice as wide or half as wide as the elements of the matched type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61834 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-18Added support for vector widening.Mon P Wang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61209 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-13Modify the intrinsics pattern to separate out the "return" types from theBill Wendling
"parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20Factor the code for determining the target-specific instructionDan Gohman
namespace out of the isel emitters and into common code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55079 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-20Fix the string for MVT::isVoid.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55034 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-30Added support for overloading intrinsics (atomics) based on pointersMon P Wang
to different address spaces. This alters the naming scheme for those intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54195 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-01Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman
the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-25Added MemOperands to Atomic operations since Atomics touches memory.Mon P Wang
Added abstract class MemSDNode for any Node that have an associated MemOperand Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and atomic.lss => atomic.load.sub git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-16- Add "Commutative" property to intrinsics. This allows tblgen to generate ↵Evan Cheng
the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-06Wrap MVT::ValueType in a struct to get type safetyDuncan Sands
and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-03Move instruction flag inference out of InstrInfoEmitter and intoDan Gohman
CodeGenDAGPatterns, where it can be used in other tablegen backends. This allows the inference to be done for DAGISelEmitter so that it gets accurate mayLoad/mayStore/isSimpleLoad flags. This brings MemOperand functionality back to where it was before 48329. However, it doesn't solve the problem of anonymous patterns which expand to code that does loads or stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49123 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-16Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb
LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-15Replace all target specific implicit def instructions with a target ↵Evan Cheng
independent one: TargetInstrInfo::IMPLICIT_DEF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-02SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng
information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-31Allow ComplexExpressions in InstrInfo.td files to be slightly more... ↵Christopher Lamb
complex! ComplexExpressions can now have attributes which affect how TableGen interprets the pattern when generating matchin code. The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46606 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner
in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-06Split the impl of CodeGenInstruction out to its own .cpp file, add a ↵Chris Lattner
getName() accessor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45645 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-05change getQualifiedName to be a global function.Chris Lattner
Split the pattern parsing code out from the dag isel emitter into it's own file. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45632 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29remove attributions from utils.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45419 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-14Add flags to indicate that there are "never" side effects or that there "may be"Bill Wendling
side effects for machine instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45022 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-13Oops. Forgot these.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44969 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-12Add a flag for indirect branch instructions.Owen Anderson
Target maintainers: please check that the instructions for your target are correctly marked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-28Add sqrt and powi intrinsics for long double.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42423 91177308-0d34-0410-b5e6-96231b3b80d8
2007-09-19Add CopyCost to TargetRegisterClass. This specifies the cost of copying a valueEvan Cheng
between two registers in the specific class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42123 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-16Add MVT::fAny for overloading intrinsics on floating-point types.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41128 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-04This is the patch to provide clean intrinsic function overloading support in ↵Chandler Carruth
LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40807 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26Add target independent MachineInstr's to represent subreg insert/extract in ↵Christopher Lamb
MBB's. PR1350 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40518 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-26Teach TableGen about the new vector types.Christopher Lamb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40513 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-20No need for noResults anymore.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40075 91177308-0d34-0410-b5e6-96231b3b80d8
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