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2011-03-02Fixes an assertion failure while disassembling ARM rsbs reg/reg form.Kevin Enderby
Patch by Ted Kremenek! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28Fix the arm's disassembler for blx that was building an MCInst without theKevin Enderby
needed two predicate operands before the imm operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126662 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23Fixed a bug in the enhanced disassembler that causedSean Callanan
it to ignore valid uses of FS and GS as additional base registers in address computations. Added a test case for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126302 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22Added a testcase for the enhanced disassembly bugSean Callanan
fixed in r126147, where a field in the X86 decode structure was being read as bits, not bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18Add assembly parsing support for "msr" and also fix its encoding. Also addBruno Cardoso Lopes
testcases for the disassembler to make sure it still works for "msr". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-14Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes
- Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-08Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson
(which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-28PR9030: Fix disassembly of ARM "mov pc, lr" instruction.Bob Wilson
Patch by Jyun-Yan You. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124492 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-13As far as I can tell, unified syntax uses c0-c15 instead of cr0-cr15 for mcr ↵Owen Anderson
and friends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06Correctly disassemble truncated asm.Rafael Espindola
Patch by Richard Simth. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122962 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-20Teach the MBlaze disassembler to disassemble special purpose registers.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122269 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-07Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson
gazillion places that need to know about it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-03When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's theJim Grosbach
32-bit wide version by adding the .w suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120838 91177308-0d34-0410-b5e6-96231b3b80d8
2010-12-01Add correct encodings for STRD and LDRD, including fixup support. ↵Owen Anderson
Additionally, update these to unified syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17Now that the MBlaze backend is in its own directory, split the test cases ↵Wesley Peck
into multiple files for different types of instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119580 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14Segregate tests by target.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13Fixed error and re-enabled MBlaze MC disassembler tests.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13This test stops after disassembling 1 instructions onDale Johannesen
darwin and, judging from the buildbots, Linux. Removing it for now, but this is not the right fix, Wesley please look at it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118977 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-13Add test cases that should have been committed with 118969.Wesley Peck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02chase owen.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118124 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02tweak this to pass.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02temporarily xfail this.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118120 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-22Fixed handling of immediate operand sizes, whichSean Callanan
weren't properly reflecting the OperandSize attribute of the instruction leading to improper decoding of certain instructions with the 66H prefix. Also added a test case for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117084 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-15ARM instructions that are both predicated and set the condition codesBob Wilson
have been printed with the "S" modifier after the predicate. With ARM's unified syntax, they are supposed to go in the other order. We fixed this for Thumb when we switched to unified syntax but missed changing it for ARM. Apparently we don't generate these instructions often because no one noticed until now. Thanks to Bill Wendling for the testcase! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-13Refactor the ARM 'setend' instruction pattern. Use a single instruction patternJim Grosbach
and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-05Added a testcase for the ENTER instruction.Sean Callanan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115580 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17Fix vmov.f64 disassembly on targets where sizeof(long) != 8.Benjamin Kramer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15add a test of an edge case value for the FP immediate (needs all digits ofJim Grosbach
precision) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114028 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to registerJim Grosbach
moves. Previously, the immediate was printed as the encoded integer value, which is incorrect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114021 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-14Reapply r113875 with additional cleanups.Jim Grosbach
"The register specified for a dregpair is the corresponding Q register, so to get the pair, we need to look up the sub-regs based on the qreg. Create a lookup function since we don't have access to TargetRegisterInfo here to be able to use getSubReg(ARM::dsub_[01])." Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use the dregpair modifier for the 2xdreg versions. Explicitly specifying the two registers as operands is more correct and more consistent with the other instruction patterns. This enables further cleanup of special case code in the disassembler as a nice side-effect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-17Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoidBob Wilson
printing "lsl #0". This fixes the remaining parts of pr7792. Make corresponding changes for encoding/decoding these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13Add a Thumb2 t2RSBrr instruction for disassembly only.Bob Wilson
This fixes another part of PR7792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111057 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-13Move the Thumb2 SSAT and USAT optional shift operator out of theBob Wilson
instruction opcode. This fixes part of PR7792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen
the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110951 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-12The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .tdJohnny Chen
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2. Recover by looking for ARM:USAT encoding pattern before delegating to the auto- gened decoder. Added a "usat" test case to arm-tests.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110894 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.Johnny Chen
Added two test cases to arm-tests.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-11Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson
instruction opcode. This also fixes part of PR7792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05Add an ARM RSCrr instruction for disassembly only.Bob Wilson
Partial fix for PR7792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110361 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05Add an ARM RSBrr instruction for disassembly only.Bob Wilson
Partial fix for PR7792. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110358 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-05ARM "rrx" shift operands do not have an immediate. PR7790.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110292 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-31Add support for disassembling VMVN (immediate) instructions. PR7747.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-13my work on adding segment registers to LEA missed the Chris Lattner
disassembler. Remove some code from the disassembler to compensate, unbreaking disassembly of lea's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06Eliminated the classification of control registers into %ecr_Sean Callanan
and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-21Thumb instructions which have reglist operands at the end and predicate operandsJohnny Chen
before reglist were not properly handled with respect to IT Block. Fix that by creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those instructions for disassembly. Add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20When doing Thumb disassembly, there's no need to consider ↵Johnny Chen
t2ADDrSPi12/t2SUBrSPi12, as their generic counterparts t2ADDri12/t2SUBri12 should suffice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if ↵Johnny Chen
Rn(Inst{19-16})=='1111', transform the Opcode to the corresponding t2LDR*pci counterpart. Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1Johnny Chen
Pseudocode details of conditional, Condition bits '111x' indicate the instruction is always executed. That is, '1111' is a leagl condition field value, which is now mapped to ARMCC::AL. Also add a test case for condition field '1111'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-19ARM disassembler did not react to recent changes to the NEON instruction table.Johnny Chen
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17testcase for r101538, patch by Nico Schmidt!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-16Minor change to make the test case comply with Vd<0> == '0' when Q == '1'.Johnny Chen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101559 91177308-0d34-0410-b5e6-96231b3b80d8
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