| Age | Commit message (Expand) | Author |
|---|
| 2010-08-11 | Fix test and re-enable it. | Evan Cheng |
| 2010-08-11 | Temporarily disable some failing tests, until they can be | Dan Gohman |
| 2010-08-11 | cortex m4 has floating point support, but only single precision. | Jim Grosbach |
| 2010-08-11 | Temporarily disable some failing tests, until they can be | Dan Gohman |
| 2010-08-11 | Consider this code snippet: | Bill Wendling |
| 2010-08-11 | Report error if codegen tries to instantiate a ARM target when the cpu does s... | Evan Cheng |
| 2010-08-11 | Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) | Evan Cheng |
| 2010-08-11 | Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit | Evan Cheng |
| 2010-08-11 | - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the | Evan Cheng |
| 2010-08-11 | Update test to match output of optimize compares for ARM. | Bill Wendling |
| 2010-08-10 | The optimize comparisons pass removes the "cmp" instruction this is checking ... | Bill Wendling |
| 2010-08-10 | Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function... | Evan Cheng |
| 2010-08-10 | Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP | Daniel Dunbar |
| 2010-08-10 | Fix test for more architectures. Patch by Tobias Grosser. | Jakob Stoklund Olesen |
| 2010-08-10 | Fix failing testcase. | Tobias Grosser |
| 2010-08-10 | Handle TAG_constant for integers. | Devang Patel |
| 2010-08-10 | Fix ARM hasFP() semantics. It should return true whenever FP register is | Evan Cheng |
| 2010-08-09 | Have SPU handle halfvec stores aligned by 8 bytes. | Kalle Raiskila |
| 2010-08-07 | Use sdmem and sse_load_f64 (etc.) for the vector | Dale Johannesen |
| 2010-08-06 | Fix eabi calling convention when a 64 bit value shadows r3. | Rafael Espindola |
| 2010-08-05 | Add an option to always emit realignment code for a particular module. | Eric Christopher |
| 2010-08-05 | Move x86 specific tests into test/CodeGen/X86. | Devang Patel |
| 2010-08-05 | Move x86-specific tests out of test/Transforms/LoopStrengthReduce and | Dan Gohman |
| 2010-08-05 | tests: CodeGen/X86/GC tests require X86. | Daniel Dunbar |
| 2010-08-04 | The lower invoke pass needs to have unreachable code elimination run after it | Bill Wendling |
| 2010-08-04 | PR7814: Truncates cannot be ignored for signed comparisons. | Eli Friedman |
| 2010-08-04 | Testcase for r110248. | Bill Wendling |
| 2010-08-04 | call-imm.ll test case regex fix. Patch by Dimitry Andric! | Stuart Hastings |
| 2010-08-04 | Make SPU backend handle insertelement and | Kalle Raiskila |
| 2010-08-04 | Combine NEON VABD (absolute difference) intrinsics with ADDs to make VABA | Bob Wilson |
| 2010-08-03 | OK, that's it. This test is going away now. But don't worry, I am taking it to a | Jakob Stoklund Olesen |
| 2010-08-02 | More SPU v2f32 stuff added: insertelement and shuffle. | Kalle Raiskila |
| 2010-08-02 | Add preliminary v2f32 support for SPU. Like with v2i32, we just | Kalle Raiskila |
| 2010-08-02 | Add preliminary v2i32 support for SPU backend. As there are no | Kalle Raiskila |
| 2010-08-02 | PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR. | Eli Friedman |
| 2010-08-01 | PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually | Eli Friedman |
| 2010-07-31 | Revert new AVX intrinsic tests. They are breaking buildbots and Bruno is | Bob Wilson |
| 2010-07-30 | A *bunch* of tests for AVX intrinsics | Bruno Cardoso Lopes |
| 2010-07-30 | Fix for bug reported by Evzen Muller on llvm-commits: make sure to correctly | Eli Friedman |
| 2010-07-30 | Many Thumb2 instructions can reference the full ARM register set (i.e., | Jim Grosbach |
| 2010-07-29 | Implement vector constants which are splat of | Dale Johannesen |
| 2010-07-28 | Implement a vectorized algorithm for <16 x i8> << <16 x i8> | Nate Begeman |
| 2010-07-27 | ~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller ... | Nate Begeman |
| 2010-07-27 | Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECT... | Nate Begeman |
| 2010-07-26 | Currently EH lowering code expects typeinfo to be global only. | Anton Korobeynikov |
| 2010-07-23 | - Allow target to specify when is register pressure "too high". In most cases, | Evan Cheng |
| 2010-07-23 | Use the proper type for shift counts. This fixes a bootstrap error. | Dan Gohman |
| 2010-07-23 | DAGCombine (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits | Dan Gohman |
| 2010-07-22 | Custom lower the memory barrier instructions and add support | Eric Christopher |
| 2010-07-21 | More register pressure aware scheduling work. | Evan Cheng |
