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2010-11-12Add conditional mvn instructions.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12Add some missing isel predicates on def : pat patterns to avoid generating ↵Evan Cheng
VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118922 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12Emacs auto-fill bug.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118908 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12Test case for PR8287: SD scheduling time. Fixed in r118904.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118906 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12Fix memory access lowering on SPU, addingKalle Raiskila
support for the case where alignment<value size. These cases were silently miscompiled before this patch. Now they are overly verbose -especially storing is- and any front-end should still avoid misaligned memory accesses as much as possible. The bit juggling algorithm added here probably has some room for improvement still. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118889 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-12Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118864 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-11Remove the memmove->memcpy optimization from CodeGen. MemCpyOpt does this.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-10Add a test to the previous added clo instruction. Patch by Akira againBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118668 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Do not use MEMBARRIER_MCR for any Thumb code.Bob Wilson
It is only supported for ARM code. Normally Thumb2 code would use DMB instead, but depending on how the compiler is invoked (e.g., -mattr=-db) that might be disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that situation. Radar 8644195 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Testcase for PR8211 (llc crash at -O0).Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118509 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shlDan Gohman
in order to fold it into a load. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118471 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Delete an extraneous svn:executable property.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118470 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-09Fix an inline asm pasto from 117667; was preventingDale Johannesen
{i64, i64} from matching i128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118465 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Add support for ARM's specialized vector-compare-against-zero instructions.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Revert 118422 in search of bot verdancy.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118429 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-08Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.Jason W Kim
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06go to great lengths to work around a GAS bug my previous patchChris Lattner
exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-05Add codegen and encoding support for the immediate form of vbic.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118291 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04When passing a huge parameter using the byval mechanism, a longDuncan Sands
sequence of loads and stores was being generated to perform the copy on the x86 targets if the parameter was less than 4 byte aligned, causing llc to use up vast amounts of memory and time. Use a "rep movs" form instead. PR7170. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118260 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04Fix @llvm.prefetch isel. Selecting between pld / pldw using the first ↵Evan Cheng
immediate rw. There is currently no intrinsic that matches to pli. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Covert VORRIMM to be produced via early target-specific DAG combining, ↵Owen Anderson
rather than legalization. This is both the conceptually correct place for it, as well as allowing it to be more aggressive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Add support for code generation of the one register with immediate form of vorr.Owen Anderson
We could be more aggressive about making this work for a larger range of constants, but this seems like a good start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Fix test.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118187 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03This test assumes SSE is present; that is not the defaultDale Johannesen
on non-X86 hosts. Hopefully fixes ppc-host buildbot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118182 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Add codegen patterns for VST1-lane instructions. Radar 8599955.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Check for extractelement with a variable operand for the element number.Bob Wilson
For NEON we had been assuming this was always an immediate constant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Fix preload instruction isel. Only v7 supports pli, and only v7 with mp ↵Evan Cheng
extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Fix DAGCombiner to avoid going into an infinite loop when itDan Gohman
encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff). This fixes rdar://8606584. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118143 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03Two sets of changes. Sorry they are intermingled.Evan Cheng
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to "optimize for latency". Call instructions don't have the right latency and this is more likely to use introduce spills. 2. Fix if-converter cost function. For ARM, it should use instruction latencies, not # of micro-ops since multi-latency instructions is completely executed even when the predicate is false. Also, some instruction will be "slower" when they are predicated due to the register def becoming implicit input. rdar://8598427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02Inline asm mult-alt constraint tests.John Thompson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118107 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02Revert r114340 (improvements in Darwin function prologue/epilogue), as it brokeJim Grosbach
assumptions about stack layout. Specifically, LR must be saved next to FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02Use frameindex, if available, as a last resort to emit debug info for a ↵Devang Patel
parameter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118020 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Add support for alignment operands on VLD1-lane instructions.Bob Wilson
This is another part of the fix for Radar 8599955. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Add VLD1-lane testcases for quad-register types.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117975 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01When we look at instructions to convert to setting the 's' flag, we need to lookBill Wendling
at more than those which define CPSR. You can have this situation: (1) subs ... (2) sub r6, r5, r4 (3) movge ... (4) cmp r6, 0 (5) movge ... We cannot convert (2) to "subs" because (3) is using the CPSR set by (1). There's an analogous situation here: (1) sub r1, r2, r3 (2) sub r4, r5, r6 (3) cmp r4, ... (5) movge ... (6) cmp r1, ... (7) movge ... We cannot convert (1) to "subs" because of the intervening use of CPSR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01NEON does not support truncating vector stores. Radar 8598391.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when theBill Wendling
peephole optimizer is disabled. That's not good at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117905 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01Disable because peephole is disabled.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117903 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30Overhaul memory barriers in the ARM backend. Radar 8601999.Bob Wilson
There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29Teach machine cse to eliminate instructions with multiple physreg uses and ↵Evan Cheng
defs. rdar://8610857. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29Remove DAG combiner patch to fold vector splats. Instcombiner does it now.Bob Wilson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng
operand and one of them has a single use that is a live out copy, favor the one that is live out. Otherwise it will be difficult to eliminate the copy if the instruction is a loop induction variable update. e.g. BB: sub r1, r3, #1 str r0, [r2, r3] mov r3, r1 cmp bne BB => BB: str r0, [r2, r3] sub r3, r3, #1 cmp bne BB This fixed the recent 256.bzip2 regression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117675 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28Teach the DAG combiner to fold a splat of a splat. Radar 8597790.Bob Wilson
Also do some minor refactoring to reduce indentation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117558 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ↵Evan Cheng
to fail. Ugh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28- Assign load / store with shifter op address modes the right itinerary classes.Evan Cheng
- For now, loads of [r, r] addressing mode is the same as the [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should identify the former case and reduce the output latency by 1. - Also identify [r, r << 2] case. This special form of shifter addressing mode is "free". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28Fix pastos in handling of AVX cvttsd2si, PR8491.Dale Johannesen
Bruno, please review, but I'm pretty sure this is right. Patch by Alex Mac! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117514 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27Shifter ops are not always free. Do not fold them (especially to formEvan Cheng
complex load / store addressing mode) when they have higher cost and when they have more than one use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
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