aboutsummaryrefslogtreecommitdiff
path: root/test/CodeGen
AgeCommit message (Expand)Author
2010-11-12Add conditional mvn instructions.Evan Cheng
2010-11-12Add some missing isel predicates on def : pat patterns to avoid generating VF...Evan Cheng
2010-11-12Emacs auto-fill bug.Andrew Trick
2010-11-12Test case for PR8287: SD scheduling time. Fixed in r118904.Andrew Trick
2010-11-12Fix memory access lowering on SPU, addingKalle Raiskila
2010-11-12Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>Bruno Cardoso Lopes
2010-11-11Remove the memmove->memcpy optimization from CodeGen. MemCpyOpt does this.Dan Gohman
2010-11-10Add a test to the previous added clo instruction. Patch by Akira againBruno Cardoso Lopes
2010-11-09Do not use MEMBARRIER_MCR for any Thumb code.Bob Wilson
2010-11-09Testcase for PR8211 (llc crash at -O0).Duncan Sands
2010-11-09Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shlDan Gohman
2010-11-09Delete an extraneous svn:executable property.Dan Gohman
2010-11-09Fix an inline asm pasto from 117667; was preventingDale Johannesen
2010-11-08Add support for ARM's specialized vector-compare-against-zero instructions.Owen Anderson
2010-11-08Revert 118422 in search of bot verdancy.Dale Johannesen
2010-11-08Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.Jason W Kim
2010-11-06go to great lengths to work around a GAS bug my previous patchChris Lattner
2010-11-05Add codegen and encoding support for the immediate form of vbic.Owen Anderson
2010-11-04When passing a huge parameter using the byval mechanism, a longDuncan Sands
2010-11-04Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immedia...Evan Cheng
2010-11-03Covert VORRIMM to be produced via early target-specific DAG combining, rather...Owen Anderson
2010-11-03Add support for code generation of the one register with immediate form of vorr.Owen Anderson
2010-11-03Fix test.Evan Cheng
2010-11-03This test assumes SSE is present; that is not the defaultDale Johannesen
2010-11-03Add codegen patterns for VST1-lane instructions. Radar 8599955.Bob Wilson
2010-11-03Check for extractelement with a variable operand for the element number.Bob Wilson
2010-11-03Fix preload instruction isel. Only v7 supports pli, and only v7 with mp exten...Evan Cheng
2010-11-03Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.Evan Cheng
2010-11-03Fix DAGCombiner to avoid going into an infinite loop when itDan Gohman
2010-11-03Two sets of changes. Sorry they are intermingled.Evan Cheng
2010-11-02Inline asm mult-alt constraint tests.John Thompson
2010-11-02Revert r114340 (improvements in Darwin function prologue/epilogue), as it brokeJim Grosbach
2010-11-02Use frameindex, if available, as a last resort to emit debug info for a param...Devang Patel
2010-11-01Add support for alignment operands on VLD1-lane instructions.Bob Wilson
2010-11-01Add VLD1-lane testcases for quad-register types.Bob Wilson
2010-11-01Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.Bob Wilson
2010-11-01When we look at instructions to convert to setting the 's' flag, we need to lookBill Wendling
2010-11-01NEON does not support truncating vector stores. Radar 8598391.Bob Wilson
2010-11-01More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when theBill Wendling
2010-11-01Disable because peephole is disabled.Bill Wendling
2010-10-30Overhaul memory barriers in the ARM backend. Radar 8601999.Bob Wilson
2010-10-29Teach machine cse to eliminate instructions with multiple physreg uses and de...Evan Cheng
2010-10-29Remove DAG combiner patch to fold vector splats. Instcombiner does it now.Bob Wilson
2010-10-29Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng
2010-10-28Teach the DAG combiner to fold a splat of a splat. Radar 8597790.Bob Wilson
2010-10-28Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng
2010-10-28Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ...Evan Cheng
2010-10-28- Assign load / store with shifter op address modes the right itinerary classes.Evan Cheng
2010-10-28Fix pastos in handling of AVX cvttsd2si, PR8491.Dale Johannesen
2010-10-27Shifter ops are not always free. Do not fold them (especially to formEvan Cheng