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AgeCommit message (Expand)Author
2011-11-01Fix operand type for x86 pmadd_ub_sw intrinsic.Craig Topper
2011-10-31Fix operand type for int_x86_ssse3_phadd_sw_128 intrinsicCraig Topper
2011-10-31Test case for X86 FS/GS Base intrinsicsCraig Topper
2011-10-31Begin adding AVX2 instructions. No selection support yet other than intrinsics.Craig Topper
2011-10-31Switch new .file directive emission off by default, change llc's flag for it toNick Lewycky
2011-10-30X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift a...Benjamin Kramer
2011-10-30Fix return type for X86 mpsadbw instrinsic. The instruction takes in a vector...Craig Topper
2011-10-30Fix pr11266.Nadav Rotem
2011-10-30Stabilize the test by specifying an exact cpu targetNadav Rotem
2011-10-29Add a new DAGCombine optimization for BUILD_VECTOR.Nadav Rotem
2011-10-29Force SSE for this test.Benjamin Kramer
2011-10-29Revert r143206, as there are still some failing tests.Dan Gohman
2011-10-28test/CodeGen/PowerPC/2008-10-17-AsmMatchingOperands.ll: [PR11218] Mark "REQUI...NAKAMURA Takumi
2011-10-28Reapply r143177 and r143179 (reverting r143188), with schedulerDan Gohman
2011-10-28Dwarf: [PR11022] Fix emitting DW_AT_const_value(>i64), to be host-endian-neut...NAKAMURA Takumi
2011-10-28test/CodeGen/X86/2010-08-10-DbgConstant.ll: Add explicit -mtriple=i686-linux....NAKAMURA Takumi
2011-10-28Speculatively disable Dan's commits 143177 and 143179 to see ifDuncan Sands
2011-10-28Always use the string pool, even when it makes the .o larger. This may helpNick Lewycky
2011-10-28Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUWDan Gohman
2011-10-27Remove the Alpha backend.Dan Gohman
2011-10-27Also set addrmode6 alignment when align==size.Jakob Stoklund Olesen
2011-10-27Avoid partial CPSR dependency from loop backedges. rdar://10357570Evan Cheng
2011-10-27Changed test to check for correct load size instead of shift as the shift mig...Pete Cooper
2011-10-27Teach our Dwarf emission to use the string pool.Nick Lewycky
2011-10-27Don't crash on 128-bit sdiv by constant. Found by inspection.Eli Friedman
2011-10-27A branch predicated on a constant can just FastEmit an unconditional branch.Chad Rosier
2011-10-26Run test with -verify-machineinstrs.Rafael Espindola
2011-10-26Fixes an issue reported by -verify-machineinstrs.Rafael Espindola
2011-10-26This commit introduces two fake instructions MORESTACK_RET andRafael Espindola
2011-10-26Make sure short memsets on ARM lower to stores, even when optimizing for size.Lang Hames
2011-10-26Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.Jim Grosbach
2011-10-26Revert r142530 at least temporarily while a discussion is had on llvm-commits...James Molloy
2011-10-26Revert part of r142530. The patch potentially hurts performance especiallyEvan Cheng
2011-10-25Remove the Blackfin backend.Dan Gohman
2011-10-24Remove the SystemZ backend.Dan Gohman
2011-10-24Don't crash on variable insertelement on ARM. PR10258.Eli Friedman
2011-10-24Check the visibility of the global variable before placing it into the stubsBill Wendling
2011-10-24Remove the explicit request for "Latency" scheduling from MSP430,Dan Gohman
2011-10-24Change the default scheduler from Latency to ILP, since LatencyDan Gohman
2011-10-23Completely re-write the algorithm behind MachineBlockPlacement based onChandler Carruth
2011-10-22Fix pr11193.Nadav Rotem
2011-10-21Fix pr11194. When promoting and splitting integers we need to useNadav Rotem
2011-10-21Don't hard code the desired alignment for loops -- it isn't 16-bytes onChandler Carruth
2011-10-211. Fix the widening of SETCC in WidenVecOp_SETCC. Use the correct return CC t...Nadav Rotem
2011-10-21Add loop aligning to MachineBlockPlacement based on review discussion soChandler Carruth
2011-10-21Add a very basic test for MachineBlockPlacement. This is essentially theChandler Carruth
2011-10-21Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with ...Craig Topper
2011-10-20Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(Chad Rosier
2011-10-19Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10...Evan Cheng
2011-10-19Improve code generation for vselect on SSE2:Nadav Rotem