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AgeCommit message (Expand)Author
2013-05-10R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen ...Tom Stellard
2013-05-10R600: Expand SUB for v2i32/v4i32Tom Stellard
2013-05-10R600: Expand MUL for v4i32/v2i32Tom Stellard
2013-05-10R600: Expand SRA for v4i32/v2i32Tom Stellard
2013-05-10R600: Expand vselect for v4i32 and v2i32Tom Stellard
2013-05-08R600/SI: Add lit tests for llvm.SI.imageload and llvm.SI.resinfo intrinsicsMichel Danzer
2013-05-06R600: Emit config values in register / value pairsTom Stellard
2013-05-06R600: Stop emitting the instruction type byte before each instructionTom Stellard
2013-05-06R600: Emit ISA for CALL_FS_* instructionsTom Stellard
2013-05-03R600: Expand vector or, shl, srl, and xor nodesTom Stellard
2013-05-03R600: Add pattern for SHA-256 Ma functionTom Stellard
2013-05-02R600: Signed literals are 64bits wideVincent Lejeune
2013-05-02R600: If previous bundle is dot4, PV valid chan is always XVincent Lejeune
2013-05-02R600: Add a test to check that use_kill is emittedVincent Lejeune
2013-05-02R600: Prettier asmPrint of AluVincent Lejeune
2013-04-30TBAA: remove !tbaa from testing cases if not used.Manman Ren
2013-04-30R600: fix loop-address.ll testVincent Lejeune
2013-04-30R600: use native for aluVincent Lejeune
2013-04-30R600: Add FetchInst bit to instruction defs to denote vertex/tex instructionsVincent Lejeune
2013-04-29R600: Use correct CF_END instruction on Northern Island GPUsTom Stellard
2013-04-29R600: Fix encoding of CF_END_{EG, R600} instructionsTom Stellard
2013-04-26R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTETom Stellard
2013-04-24R600: Use SHT_PROGBITS for the .AMDGPU.config sectionTom Stellard
2013-04-23R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune
2013-04-23R600: Add CF_ENDVincent Lejeune
2013-04-19R600: Add pattern for the BFI_INT instructionTom Stellard
2013-04-19R600: Reorganize lit tests and document how they should be organizedTom Stellard
2013-04-17R600: Make Export Instruction not duplicableVincent Lejeune
2013-04-15R600/SI: Emit config values in register value pairs.Tom Stellard
2013-04-15R600/SI: Emit configuration value in the .AMDGPU.config ELF sectionTom Stellard
2013-04-15R600: Emit ELF formatted code rather than raw ISA.Tom Stellard
2013-04-10R600/SI: Add pattern for AMDGPUurecipMichel Danzer
2013-04-10R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addrVincent Lejeune
2013-04-10R600/SI: dynamical figure out the reg class of MIMGChristian Konig
2013-04-10R600/SI: adjust writemask to only the used componentsChristian Konig
2013-04-10R600/SI: remove image sample writemaskChristian Konig
2013-04-05R600/SI: Add support for buffer stores v2Tom Stellard
2013-04-05R600/SI: Add processor types for each SI variantTom Stellard
2013-04-05R600/SI: Avoid generating S_MOVs with 64-bit immediates v2Tom Stellard
2013-04-04R600: Take export into account when computing cf addressVincent Lejeune
2013-04-03R600: Fix last ALU of a clause being emitted in a separate clauseVincent Lejeune
2013-04-01R600: Add support for native control flowVincent Lejeune
2013-04-01R600: Emit CF_ALU and use true kcache register.Vincent Lejeune
2013-03-27R600/SI: add SETO/SETUO patternsChristian Konig
2013-03-27R600/SI: add cummuting of rev instructionsChristian Konig
2013-03-27R600/SI: add mulhu/mulhs patternsChristian Konig
2013-03-27R600/SI: add srl/sha patterns for SIChristian Konig
2013-03-26R600/SI: mark most intrinsics as readnone v2Christian Konig
2013-03-22R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730Michel Danzer
2013-03-14R600: Factorize code handling Const Read Port limitationVincent Lejeune
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