| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2013-02-13 | For Mips 16, add the optimization where the 16 bit form of addiu sp can be used | Reed Kotler | |
| if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8 | |||
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