llvm - http://llvm.org

Age	Commit message (Collapse)	Author
2011-07-07	Change some ARM subtarget features to be single bit yes/no in order to sink ↵	Evan Cheng
	them down to MC layer. Also fix tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14	Since ARM's prefetch implementation predicted the presence of a instruction	Bruno Cardoso Lopes
	cache prefetch and now that the info from "prefetch" to "ARMPreload" is present, only add a testcase for PLI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132978 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14	Add one more argument to the prefetch intrinsic to indicate whether it's a data	Bruno Cardoso Lopes
	or instruction cache access. Update the targets to match it and also teach autoupgrade. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19	Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://8648637.	Bob Wilson
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129774 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04	Fix @llvm.prefetch isel. Selecting between pld / pldw using the first ↵	Evan Cheng
	immediate rw. There is currently no intrinsic that matches to pli. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03	Fix preload instruction isel. Only v7 supports pli, and only v7 with mp ↵	Evan Cheng
	extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03	Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.	Evan Cheng
	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8