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2011-06-03Revert name change from r132533. Lower case naming was intended per style ↵Chad Rosier
guidelines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132555 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.Roman Divacky
- Check for MTCTR8 in addition to MTCTR when looking up a hazard. - When lowering an indirect call use CTR8 when targeting 64bit. - Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND. The last change fixes PR8487. With those changes, we are able to compile a running "ls" and "sh" on FreeBSD/PowerPC64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132552 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03singed int causes signed extension, which contradicts the intention to pick upZhongxing Xu
integers with high 32 bits being zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132538 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Bail on unswitching a switch statement for a case with a critical edge. We nameNick Lewycky
which edge to split by pred/succ pair, which means that we can end up splitting the wrong edge (by case value) in the switch statement entirely. Fixes PR10031! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132535 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Whitespace and other cleanup. Functionallity unchanged.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132533 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Add ARM fast-isel support for materializing the address of a global in cases ↵Eli Friedman
where the global uses an indirect symbol. rdar://9431157 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132522 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03Basic PassManager diagnostics.Andrew Trick
Added asserts whenever attempting to use a potentially uninitialized pass. This helps people trying to develop a new pass and people trying to understand the bug reports filed by the former people. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132520 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-03whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132519 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Avoid calling TRI->getAllocatableSet in RAFast.Jakob Stoklund Olesen
When compiling a program with lots of small functions like 483.xalancbmk, this makes RAFast 11% faster. Add some comments to clarify the difference between unallocatable and reserved registers. It's quite subtle. The fast register allocator depends on EFLAGS' not being allocatable on x86. That way it can completely avoid tracking liveness, and it won't mind when there are multiple uses of a single def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132514 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher
Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Flag unallocatable register classes instead of giving them emptyJakob Stoklund Olesen
allocation orders. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132509 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Make it possible to have unallocatable register classes.Jakob Stoklund Olesen
Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Preserve line number information while converting Invoke into a Call.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132505 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Just use a SmallVector.Jakob Stoklund Olesen
I was confused whether new uint8_t[] would zero-initialize the returned array, and it seems that so is gcc-4.0. This should fix the test failures on darwin 9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132500 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Remove dead code.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132488 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Update DBG_VALUEs while breaking anti dependencies.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132487 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Fix encoding for VEXTdf.Tanya Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132486 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02PR10067: Add missing safety check to call return transformation in ↵Eli Friedman
MemCpyOpt::processStore. If something accesses the dest of the "copy" between the call and the copy, the performCallSlotOptzn transformation is not valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132485 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02During post RA scheduling, do not try to chase reg defs. to preserve ↵Devang Patel
DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132483 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Revert 132424 to fix PR10068.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132479 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Add a new parse hint for multi-letter constraints in inline asm.Eric Christopher
Testcase will come when we use it. Part of rdar://9119939 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132476 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Use RegisterClassInfo::getOrder in RAFast.Jakob Stoklund Olesen
This saves two virtual function calls and an Allocatable BitVector test, making RAFast run 2% faster. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132471 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02.cfi directive register parsing flexibility.Jim Grosbach
Parsing a register name/number for .cfi directives can't assume that a register name starts with a '%' token. Be more flexible and check for a register number instead. Still unlikely to be perfect, but it allows us to parse both plain identifiers as register names and integers as register numbers, which is what we're wanting to support at this point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132466 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Omit unnecessary stack copy when x87 input is a load.Stuart Hastings
rdar://problem/6373334 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132458 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Start with a zeroed CSRNum map.Benjamin Kramer
Found by valgrind. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132457 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Initialize members to fix problem found by valgrind.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132456 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Use TRI::has{Sub,Super}ClassEq() where possible.Jakob Stoklund Olesen
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Don't hardcode the %reg format in the streamer.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132451 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Add a RegisterClassInfo class that lazily caches information aboutJakob Stoklund Olesen
register classes. It provides information for each register class that cannot be determined statically, like: - The number of allocatable registers in a class after filtering out the reserved and invalid registers. - The preferred allocation order with registers that overlap callee-saved registers last. - The last callee-saved register that overlaps a given physical register. This information usually doesn't change between functions, so it is reused for compiling multiple functions when possible. The many possible combinations of reserved and callee saves registers makes it unfeasible to compute this information statically in TableGen. Use RegisterClassInfo to count available registers in various heuristics in SimpleRegisterCoalescing, making the pass run 4% faster. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132448 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02Custom-lower FRAMEADDR. Patch by Sasa Stankovic.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132444 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-02When marking a block as being unanalyzable, use "Clobber" on the terminator ↵Eli Friedman
instead of the first instruction in the block. This is a bit of a hack; "Clobber" isn't really the right marking in the first place. memdep doesn't really have any way of properly expressing "unanalyzable" at the moment. Using it on the terminator is much less ambiguous than using it on an arbitrary instruction, though. In the given testcase, the "Clobber" was pointing to a load, and GVN was incorrectly assuming that meant that the "Clobber" load overlapped the load being analyzed (when they are actually unrelated). The included testcase tests both this commit and r132434. Part two of rdar://9429882. (r132434 was mislabeled.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132442 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01In MemoryDependenceAnalysis::getNonLocalPointerDepFromBB, if a given block ↵Eli Friedman
is is deemed unanalyzable (and we execute one of the "goto PredTranslationFailure" statements), make sure we don't put information about the predecessors of that block into the returned data structures; this can lead to, among other things, extraneous results (which will confuse passes using memdep). Fixes an assert in GVN compiling ruby. Part of rdar://problem/9521954 . Testcase coming up soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132434 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01A DBG_VALUE that truncates a range does not start another dbg value range.Devang Patel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132433 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Do not drop constant values when a variable's content is described using ↵Devang Patel
.debug_loc entries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Recommit 132404 with fixes. rdar://problem/5993888Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Allow bitcasts between valid types of the same size and vectorEric Christopher
types if the vector type is legal. Fixes rdar://9306086 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132420 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Revert 132404 to appease a buildbot. rdar://problem/5993888Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132419 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer useNadav Rotem
the TargetLowering enum. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132418 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01SCEV: missing null check fix for r132360, dragonegg crash.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132416 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Revert r132358 "Simplify the eviction policy by making the failsafe explicit."Jakob Stoklund Olesen
This commit caused regressions in i386 flops-[568], matrix, salsa20, 256.bzip2, and enc-md5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132413 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Fix double FGETSIGN to work on x86_32; followup to 132396.Stuart Hastings
rdar://problem/5660695 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132411 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Add support for x86 CMPEQSS and friends. These instructions do aStuart Hastings
floating-point comparison, generate a mask of 0s or 1s, and generally DTRT with NaNs. Only profitable when the user wants a materialized 0 or 1 at runtime. rdar://problem/5993888 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132404 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Reapply 132348 with fixes. rdar://problem/6501862Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132402 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Fix PR10059 and future variations by handling all register subclasses.Jakob Stoklund Olesen
Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible register classes instead of trying to list all register classes in X86's getLoadStoreRegOpcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132398 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Turn on FGETSIGN for x86. Followup to 132388. rdar://problem/5660695Stuart Hastings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132396 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Add new -d option to tblgen. It writes a make(1)-style dependency file.Joerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132395 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01This patch is another step in the direction of adding vector select. In thisNadav Rotem
patch we add a flag to enable a new type legalization decision - to promote integer elements in vectors. Currently, the rest of the codegen does not support this kind of legalization. This flag will be removed when the transition is complete. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132394 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01FGETSIGN support for x86, using movmskps/pd. Will be enabled with aStuart Hastings
patch to TargetLowering.cpp. rdar://problem/5660695 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132388 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-01Add an issue width check to the postRA scheduler. Patch by Max Kazakov!Andrew Trick
For targets with no itinerary (x86) it is a nop by default. For targets with issue width already expressed in the itinerary (ARM) it bypasses a scoreboard check but otherwise does not affect the schedule. It does make the code more consistent and complete and allows new targets to specify their issue width in an arbitrary way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132385 91177308-0d34-0410-b5e6-96231b3b80d8
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