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AgeCommit message (Expand)Author
2011-10-27ARM isel for vld1, opcode selection for register stride post-index pseudos.Jim Grosbach
2011-10-27Avoid partial CPSR dependency from loop backedges. rdar://10357570Evan Cheng
2011-10-27Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix andKevin Enderby
2011-10-27Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.Jim Grosbach
2011-10-27Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.Jim Grosbach
2011-10-27A branch predicated on a constant can just FastEmit an unconditional branch.Chad Rosier
2011-10-26Rename NonScalarIntSafe to something more appropriate.Lang Hames
2011-10-26Add a TODO comment. FastISel works by parsing each basic block from the bottomChad Rosier
2011-10-26Factor a little more code into EmitCmp, which should have been done in the firstChad Rosier
2011-10-26Use EmitCmp in SelectBranch. No functional change intended.Chad Rosier
2011-10-26Factor out an EmitCmp function that can be used by both SelectCmp andChad Rosier
2011-10-26Thumb2 ldr pc-relative encoding fixes.Jim Grosbach
2011-10-26Fixes an issue reported by -verify-machineinstrs.Rafael Espindola
2011-10-26ARM parse parenthesized expressions for label references.Jim Grosbach
2011-10-26This commit introduces two fake instructions MORESTACK_RET andRafael Espindola
2011-10-26Make sure short memsets on ARM lower to stores, even when optimizing for size.Lang Hames
2011-10-26Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.Jim Grosbach
2011-10-26Revert r142530 at least temporarily while a discussion is had on llvm-commits...James Molloy
2011-10-26Use a worklist to prevent the iterator from becoming invalidated because of t...Bill Wendling
2011-10-26Revert part of r142530. The patch potentially hurts performance especiallyEvan Cheng
2011-10-25Corrects previously incorrect $sp change in MipsCompilationCallback.Bruno Cardoso Lopes
2011-10-25ARM assembly parsing and encoding for VLD1 with writeback.Jim Grosbach
2011-10-25Remove the Blackfin backend.Dan Gohman
2011-10-24Remove the SystemZ backend.Dan Gohman
2011-10-24Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.Jim Grosbach
2011-10-24ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach
2011-10-24Don't crash on variable insertelement on ARM. PR10258.Eli Friedman
2011-10-24ARMConstantPoolMBB::print should print BB number.Evan Cheng
2011-10-24ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach
2011-10-24ARM refactor am6offset usage for VLD1.Jim Grosbach
2011-10-24Add support to the old JIT for acquire/release loads and stores on x86. PR11...Eli Friedman
2011-10-24Fix a NEON disassembly case that was broken in the recent refactorings. As m...Owen Anderson
2011-10-24Change this overloaded use of Sched::Latency to be an overloadedDan Gohman
2011-10-24Remove the explicit request for "Latency" scheduling from MSP430,Dan Gohman
2011-10-24Thumb2 LDM instructions can target PC. Make sure to encode it.Jim Grosbach
2011-10-23Add X86 SARX, SHRX, and SHLX instructions.Craig Topper
2011-10-23Add X86 RORX instructionCraig Topper
2011-10-23Add X86 MULX instruction for disassembler.Craig Topper
2011-10-22Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 ...Craig Topper
2011-10-22Move various generated tables into read-only memory, fixing up const correctn...Benjamin Kramer
2011-10-22Fix pr11193.Nadav Rotem
2011-10-22The different flavors of ARM have different valid subsets of registers. CheckBill Wendling
2011-10-21Assembly parsing for 4-register sequential variant of VLD2.Jim Grosbach
2011-10-21Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach
2011-10-21Assembly parsing for 4-register variant of VLD1.Jim Grosbach
2011-10-21Assembly parsing for 3-register variant of VLD1.Jim Grosbach
2011-10-21ARM VLD parsing and encoding.Jim Grosbach
2011-10-21Don't automatically set the "fc" bits on MSR instructions if the user didn't ...Owen Anderson
2011-10-21Nuke an #if0 that got accidentally left in.Jim Grosbach
2011-10-21whitespace.Jim Grosbach