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AgeCommit message (Expand)Author
2011-11-17Dead code.Chad Rosier
2011-11-17Remove seemingly unnecessary duplicate VROUND definitions.Craig Topper
2011-11-17Add support for custom names for library functions in TargetLibraryInfo. Add...Eli Friedman
2011-11-17Don't unconditionally set the kill flag.Chad Rosier
2011-11-17Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I...Eli Friedman
2011-11-16Generalize the fixup info for ARM mode.Jim Grosbach
2011-11-16Lower 64-bit constant pool node.Akira Hatanaka
2011-11-16Lower 64-bit block address.Akira Hatanaka
2011-11-16Fix encoding of NOP used for padding in ARM mode .align.Jim Grosbach
2011-11-16Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpoolAkira Hatanaka
2011-11-1664-bit jump register instruction.Akira Hatanaka
2011-11-16Another missing X86ISD::MOVLPD pattern. rdar://10450317Evan Cheng
2011-11-16ARM assembly parsing for shifted register operands for MOV instruction.Jim Grosbach
2011-11-16Clean up debug printing of ARM shifted operands.Jim Grosbach
2011-11-16ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.Jim Grosbach
2011-11-16ARM assembly parsing for RRX mnemonic.Jim Grosbach
2011-11-16Added missing comment about new custom lowering of DEC64Pete Cooper
2011-11-16Check to make sure we can select the instruction before trying to put theChad Rosier
2011-11-16ARM mode aliases for bitwise instructions w/ register operands.Jim Grosbach
2011-11-16Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.Bob Wilson
2011-11-16lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp al...NAKAMURA Takumi
2011-11-16Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng
2011-11-16Fix the execution domain on a bunch of SSE/AVX instructions.Craig Topper
2011-11-16Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>Bob Wilson
2011-11-16Remove code to enable execution dependency fix pass on VR256. VR128 is suffic...Craig Topper
2011-11-16Add FIXME comment.Chad Rosier
2011-11-15Enable -widen-vmovs by default.Jakob Stoklund Olesen
2011-11-15ARM assembly parsing for register range syntax for VLD/VST register lists.Jim Grosbach
2011-11-15ARM assembly parsing for data type suffices on NEON VMOV aliases.Jim Grosbach
2011-11-15AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the vb...Nadav Rotem
2011-11-15ARM assembly parsing two operand forms for shift instructions.Jim Grosbach
2011-11-15ARM VFP assembly parsing for VADD and VSUB two-operand forms.Jim Grosbach
2011-11-15ARM accept an immediate offset in memory operands w/o the '#'.Jim Grosbach
2011-11-15Added custom lowering for load->dec->store sequence in x86 when the EFLAGS re...Pete Cooper
2011-11-15ARM enclosing curly braces optional on one-register VLD/VST instruction lists.Jim Grosbach
2011-11-15ARM size suffix on VFP single-precision 'vmov' is optional.Jim Grosbach
2011-11-15Fix typo.Jim Grosbach
2011-11-15ARM alternate size suffices for VTRN instructions.Jim Grosbach
2011-11-15Fix a misplaced paren bug.Owen Anderson
2011-11-15ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.Jim Grosbach
2011-11-15ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach
2011-11-15ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach
2011-11-15Thumb2 two-operand 'mul' instruction wide encoding parsing.Jim Grosbach
2011-11-15Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VM...Owen Anderson
2011-11-15Thumb2 assembly parsing for mul.w in IT block fix.Jim Grosbach
2011-11-15Fix functions in MipsFrameLowering.cpp and MipsRegisterInfo.cpp. Use 64-bitAkira Hatanaka
2011-11-15Set nomacro before emitting the sequence of instructions that set global pointerAkira Hatanaka
2011-11-15Simplify function PassByValArg64.Akira Hatanaka
2011-11-15Delete files.Akira Hatanaka
2011-11-15Remove MipsMCSymbolRefExpr.Akira Hatanaka
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