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AgeCommit message (Expand)Author
2012-01-25ARM assemly parsing and validation of IT instruction.Jim Grosbach
2012-01-25fix a bug I introduced in r148929, this is not a splat!Chris Lattner
2012-01-25Custom lower PSIGN and PSHUFB intrinsics to their corresponding target specif...Craig Topper
2012-01-25use ConstantVector::getSplat in a few places.Chris Lattner
2012-01-25Custom lower phadd and phsub intrinsics to target specific nodes. Remove the ...Craig Topper
2012-01-25Remove AVX 256-bit unaligned load intrinsics. 128-bit versions had been remov...Craig Topper
2012-01-25Mark 64-bit register RA_64 unused too.Akira Hatanaka
2012-01-25Modify MipsFrameLowering::emitPrologue and emitEpilogue.Akira Hatanaka
2012-01-25Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate toAkira Hatanaka
2012-01-25Merge intrinsic pattern and no pattern versions of VCVTSD2SI intruction defin...Craig Topper
2012-01-25MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc.NAKAMURA Takumi
2012-01-25Target/Mips: Unbreak CMake build.NAKAMURA Takumi
2012-01-25Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. Akira Hatanaka
2012-01-25Add class MipsAnalyzeImmediate which comes up with an instruction sequence toAkira Hatanaka
2012-01-25NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach
2012-01-24Tidy up. Rename VLD4DUP patterns for consistency.Jim Grosbach
2012-01-24NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach
2012-01-24Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,Akira Hatanaka
2012-01-24Pass CCState by reference.Akira Hatanaka
2012-01-24Pattern for f32 to i64 conversion.Akira Hatanaka
2012-01-24Intel Syntax: Extend special hand coded logic, to recognize special instructi...Devang Patel
2012-01-2464-bit sign extension in register instructions.Akira Hatanaka
2012-01-24NEON VST4(one lane) assembly parsing and encoding.Jim Grosbach
2012-01-24Widen the instruction encoder that TblGen emits to a 64 bits, which should ac...Owen Anderson
2012-01-24NEON VLD4(one lane) assembly parsing and encoding.Jim Grosbach
2012-01-24NEON Two-operand assembly aliases for VSRA.Jim Grosbach
2012-01-24NEON Two-operand assembly aliases for VSLI.Jim Grosbach
2012-01-24NEON Two-operand assembly aliases for VSRI.Jim Grosbach
2012-01-24NEON add correct predicates for some asm aliases.Jim Grosbach
2012-01-24C++, CBE, and TLOF support for ConstantDataSequentialChris Lattner
2012-01-24ZERO_EXTEND operation is optimized for AVX.Elena Demikhovsky
2012-01-24Use correct register class for am2offset register operands.Anton Korobeynikov
2012-01-24Add comments near load pattern fragments indicating that all integer vector l...Craig Topper
2012-01-24NEON VST4(multiple 4 element structures) assembly parsing.Jim Grosbach
2012-01-24NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach
2012-01-24Tidy up. Remove some vertical space for readability.Jim Grosbach
2012-01-24Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth
2012-01-24Fix typo.Jim Grosbach
2012-01-24NEON VST3(single element from one lane) assembly parsing.Jim Grosbach
2012-01-23Fix typo. Devang Patel
2012-01-23NEON VST3(multiple 3-element structures) assembly parsing.Jim Grosbach
2012-01-23NEON VLD3(multiple 3-element structures) assembly parsing.Jim Grosbach
2012-01-23Add missed mayStore flag to STREXD / t2STREXDAnton Korobeynikov
2012-01-23Intel syntax: Robustify parsing of memory operand's displacement experssion.Devang Patel
2012-01-23NEON VLD3 lane-indexed assembly parsing and encoding.Jim Grosbach
2012-01-23Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]Devang Patel
2012-01-23Simplify some NEON assembly pseudo definitions.Jim Grosbach
2012-01-23Intel syntax: Parse segment registers.Devang Patel
2012-01-23ARMAsmPrinter.cpp: Try to fix up r148686. EnableARMEHABI was also here.NAKAMURA Takumi
2012-01-23Custom lower PCMPEQ/PCMPGT intrinsics to target specific nodes and remove the...Craig Topper
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