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AgeCommit message (Expand)Author
2012-05-11Typo.Chad Rosier
2012-05-11[fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Min...Chad Rosier
2012-05-11Hexagon V5 intrinsics support.Sirish Pande
2012-05-11[fast-isel] Cleaner fix for when we're unable to handle a non-double multi-regChad Rosier
2012-05-11[fast-isel] Rather then assert (or segfault in a non-asserts build), fall backChad Rosier
2012-05-11The return type is an unsigned, not a bool.Chad Rosier
2012-05-11Add space before an open parenthesis in control flow statements.Manman Ren
2012-05-11Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd
2012-05-11Implement initial-exec TLS model for 32-bit PIC x86Hans Wennborg
2012-05-11Added the missing bit definition for the 4th bit of the STR (post reg) instru...Silviu Baranga
2012-05-11Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate o...Silviu Baranga
2012-05-11Fix a misleading comment.Akira Hatanaka
2012-05-11ARM: peephole optimization to remove cmp instructionManman Ren
2012-05-11Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(),Dan Gohman
2012-05-10Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd
2012-05-10Add support for the 'X' inline asm operand modifier.Eric Christopher
2012-05-10Hexagon V5 Support - V5 td file.Sirish Pande
2012-05-10Hexagon V5 FP Support.Sirish Pande
2012-05-10Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren
2012-05-10ARM: peephole optimization to remove cmp instructionManman Ren
2012-05-10Fix merge-typo and cleanupNadav Rotem
2012-05-10AVX2: Add an additional broadcast idiom.Nadav Rotem
2012-05-10Generate AVX/AVX2 shuffles even when there is a memory op somewhere else in t...Nadav Rotem
2012-05-09Mark .opd @progbits, thus avoiding a warning from asm.Roman Divacky
2012-05-09Add another peephole pattern for conditional moves.Akira Hatanaka
2012-05-09Use ptr_rc_tailcall instead of GR32_TC.Jakob Stoklund Olesen
2012-05-09Make register FP allocatable if the compiled function does not have dynamicAkira Hatanaka
2012-05-09Expand 64-bit shifts if target ABI is O32.Akira Hatanaka
2012-05-09Remove unused variable to silence compiler warning.Richard Trieu
2012-05-08Use a shared function for a common operation.Jakob Stoklund Olesen
2012-05-08Remove excess semi-colons to quiet warnings.Eric Christopher
2012-05-08Update load/store instruction patterns in Hexagon V4.Sirish Pande
2012-05-08Define mips16 instruction formats.Akira Hatanaka
2012-05-08s/CSR_Ghc/CSR_NoRegs/Jakob Stoklund Olesen
2012-05-08Remove 256-bit AVX non-temporal store intrinsics. Similar was previously done...Craig Topper
2012-05-07Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen
2012-05-07Fix bug in TRI::getCommonSuperRegClass().Jakob Stoklund Olesen
2012-05-07Add TRI::getCommonSuperRegClass().Jakob Stoklund Olesen
2012-05-07Fix a regression from r147481. This combine should only happen if there is aChad Rosier
2012-05-07X86: optimization for -(x != 0)Manman Ren
2012-05-07Add support for the 'x' constraint.Eric Christopher
2012-05-07Add support for the 'l' constraint.Eric Christopher
2012-05-07Add support for the 'c' constraint.Eric Christopher
2012-05-07Add support for the 'P' constraint.Eric Christopher
2012-05-07Fix some issues in the f16c instructions.Craig Topper
2012-05-07Add support for the 'O' constraint.Eric Christopher
2012-05-07Add support for the 'N' inline asm constraint.Eric Christopher
2012-05-07Add support for the 'L' inline asm constraint.Eric Christopher
2012-05-07Add support for the inline asm constraint 'K'.Eric Christopher
2012-05-07Add SSE4A MOVNTSS/MOVNTSD instructions.Craig Topper
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