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AgeCommit message (Expand)Author
2012-06-07X86: optimize generated code for integer ABSManman Ren
2012-06-07Do not optimize the used bits of the x86 vselect condition operand, when the ...Nadav Rotem
2012-06-07Continue factoring computeOperandLatency. Use it for ARM hasHighOperandLatency.Andrew Trick
2012-06-07ARM getOperandLatency rewrite.Andrew Trick
2012-06-07ARM getOperandLatency should return -1 for unknown, consistent with APIAndrew Trick
2012-06-07Fix ARM getInstrLatency logic to work with the current API.Andrew Trick
2012-06-07PR13046: we can't replace usage of SUB with CMP in the lowering phase.Manman Ren
2012-06-07Use a base register instead of an index register with the local dynamic model.Rafael Espindola
2012-06-07X86: replace SUB with CMP if possibleManman Ren
2012-06-06Revert r157755.Manman Ren
2012-06-06Round 2 of dead private variable removal.Benjamin Kramer
2012-06-06Remove unused private fields found by clang's new -Wunused-private-field.Benjamin Kramer
2012-06-06Add support for dynamic stack realignment in the presence of dynamic allocas onChad Rosier
2012-06-06Correct decoder for T1 conditional B encodingRichard Barton
2012-06-06Mark several instructions SSE2 instead of SSE3 as they should be.Craig Topper
2012-06-05misched: API for minimum vs. expected latency.Andrew Trick
2012-06-05Fix header file include order in NVPTX backend NV_CONTRIBYuan Lin
2012-06-05PPC32 uses R2 as the TLS register. Fix the copy and paste.Roman Divacky
2012-06-05X86 itinerary properties.Andrew Trick
2012-06-05ARM itinerary properties.Andrew Trick
2012-06-05misched: Added MultiIssueItineraries.Andrew Trick
2012-06-05whitespaceAndrew Trick
2012-06-05Revert commit r157966Joel Jones
2012-06-04This change handles a another case for generating the bic instruction Joel Jones
2012-06-04Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node isAkira Hatanaka
2012-06-04Implement local-exec TLS on PowerPC.Roman Divacky
2012-06-04MIPS TLS: use the model selected by TargetMachine::getTLSModel().Hans Wennborg
2012-06-04Better comments for TLS-related X86 MachineOperand flags.Hans Wennborg
2012-06-04Add intrinsic forms for FMA instructions to opcode folding tables.Craig Topper
2012-06-04Add VFMADDSUB and VFMSUBADD FMA instructions to folding tables. Also add 213 ...Craig Topper
2012-06-04Fix a copy-and-paste duplication error in the PPC 440 and A2 schedules (no fu...Hal Finkel
2012-06-04Enable generating PPC pre-increment (r+imm) instructions by default.Hal Finkel
2012-06-03Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.Craig Topper
2012-06-03Rename fma4 intrinsics to just fma since they are now used for both FMA4 and ...Craig Topper
2012-06-03Revert r157831Manman Ren
2012-06-03Use sse_load_f32/64 for scalar FMA3 intrinsic patterns instead of 128-bit loa...Craig Topper
2012-06-03Add neverHasSideEffects and mayLoad to FMA3 instructions.Craig Topper
2012-06-02Fix typos found by http://github.com/lyda/misspell-checkBenjamin Kramer
2012-06-02remove an unused variable.Chris Lattner
2012-06-02Remove code which is no longer needed in MipsAsmPrinter and MipsMCInstLower.Akira Hatanaka
2012-06-02Set operation actions for load/store nodes in the Mips backend.Akira Hatanaka
2012-06-02Add definitions of 32/64-bit unaligned load/store instructions for Mips.Akira Hatanaka
2012-06-02Define functions MipsTargetLowering::LowerLOAD and LowerSTORE whichAkira Hatanaka
2012-06-02Define Mips specific unaligned load/store nodes.Akira Hatanaka
2012-06-02Expand unaligned i16 loads/stores for the Mips backend.Akira Hatanaka
2012-06-02In MipsMCInstLower::LowerSymbolOperand, get offset from symbol ifAkira Hatanaka
2012-06-01Switch all register list clients to the new MC*Iterator interface.Jakob Stoklund Olesen
2012-06-01[arm-fast-isel] Fix handling of the frameaddress intrinsic. If depth is 0Chad Rosier
2012-06-01Switch some getAliasSet clients to MCRegAliasIterator.Jakob Stoklund Olesen
2012-06-01X86: peephole optimization to remove cmp instructionManman Ren
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