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2013-04-16Remove unused variable from previous refactor.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179611 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16[ms-inline asm] Refactor. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179610 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16[ms-inline asm] Remove some dead code.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179607 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16Fix build failure introduced in 179591 when assertions are disabled.Logan Chien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179593 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16Implement ARM unwind opcode assembler.Logan Chien
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179591 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-16Add 64-bit multiply and divide instructions for SPARC v9.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179582 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15ARM: Add VACLT and VACLE assembly aliases.Jim Grosbach
These are aliases for VACGT and VACGE, respectively, with the source operands reversed. rdar://13638090 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179575 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Mips assembler: Explicit floating point condition register recognition.Jack Carter
This patch allows the assembler to recognize $fcc0 as a valid register for conditional move instructions. Corresponding test cases have been added. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15R600/SI: Emit config values in register value pairs.Tom Stellard
Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15R600/SI: Emit configuration value in the .AMDGPU.config ELF sectionTom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179545 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15R600: Emit ELF formatted code rather than raw ISA.Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179544 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Mark all PPC comparison instructions as not having side effectsHal Finkel
Now that the CR spilling issues have been resolved, we can remove the unmodeled-side-effect attributes from the comparison instructions (and also mark them as isCompare). By allowing these, by default, to have unmodeled side effects, we were hiding problems with CR spilling; but everything seems much happier now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179502 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15Fix PPC64 CR spill location for callee-saved registersHal Finkel
This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition registers, the spill location is specified relative to the stack pointer (SP + 8). However, this is not relative to the SP after the new stack frame is established, but instead relative to the caller's stack pointer (it is stored into the linkage area of the parent's stack frame). So, like with the link register, we don't directly spill the CRs with other callee-saved registers, but just mark them to be spilled during prologue generation. In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179500 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Use i32 for all SPARC shift amounts, even in 64-bit mode.Jakob Stoklund Olesen
Test case by llvm-stress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179477 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Add support for the abs64 SPARC v9 code model.Jakob Stoklund Olesen
For when 16 TB just isn't enough. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179474 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Add support for the SPARC v9 abs44 code model.Jakob Stoklund Olesen
This is the default model for non-PIC 64-bit code. It supports text+data+bss linked anywhere in the low 16 TB of the address space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179473 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Use target flags for printing SPARC asm operands.Jakob Stoklund Olesen
64-bit code models need multiple relocations that can't be inferred from the opcode like they can in 32-bit code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179472 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Also put target flags on SPARC constant pool references.Jakob Stoklund Olesen
Constant pool entries are accessed exactly the same way as global variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Fix patterns for 64-bit pointers.Jakob Stoklund Olesen
This fixes the pic32 code model for SPARC v9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179469 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14Add target flags to SPARC address operands.Jakob Stoklund Olesen
SDNodes and MachineOperands get target flags representing the %hi() and %lo() assembly annotations that eventually become relocations. Also define flags to be used by the 64-bit code models. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179468 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13Mark all PPC CR registers to be spilled as live-in and tag MFCR appropriatelyHal Finkel
Leaving MFCR has having unmodeled side effects is not enough to prevent unwanted instruction reordering post-RA. We could probably apply a stronger barrier attribute, but there is a better way: Add all (not just the first) CR to be spilled as live-in to the entry block, and add all CRs to the MFCR instruction as implicitly killed. Unfortunately, I don't have a small test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179465 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13Define SPARC code models.Jakob Stoklund Olesen
Currently, only abs32 and pic32 are implemented. Add a test case for abs32 with 64-bit code. 64-bit PIC code is currently broken. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179463 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13Use the correct types when matching ADDRri patterns from frame indexes.Jakob Stoklund Olesen
It doesn't seem like anybody is checking types this late in isel, so no test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179462 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13Spill and restore PPC CR registers using the FP when we have oneHal Finkel
For functions that need to spill CRs, and have dynamic stack allocations, the value of the SP during the restore is not what it was during the save, and so we need to use the FP in these cases (as for all of the other spills and restores, but the CR restore has a special code path because its reserved slot, like the link register, is specified directly relative to the adjusted SP). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179457 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13X86 machine model: reduce SandyBridge and Haswell ILPWindow.Andrew Trick
The initial values were arbitrary. I want them to be more conservative. This represents the number of latency cycles hidden by OOO execution. In practice, I think it should be within a small factor of the complex floating point operation latency so the scheduler can make some attempt to hide latency even for smallish blocks. These are by no means the best values, just a starting point for tuning heuristics. Some benchmarks such as TSVC run faster with this lower value for SandyBridge. I haven't run anything on Haswell, but it's shouldn't be 2x SB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179450 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13Catch another case where SD fails to propagate node order.Andrew Trick
I need to handle this for the test case in my following scheduler commit. Work is already under way to redesign the mechanism for node order propagation because this case by case approach is unmaintainable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179448 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13[mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN andAkira Hatanaka
lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179444 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13[mips] Reapply r179420 and r179421.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179434 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-13[mips] Override TargetLoweringBase::isShuffleMaskLegal.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179433 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12[ms-inline asm] Simplify the logic by using parsePrimaryExpr. No functionalChad Rosier
change intended. Test case previously added in r178568. Part of rdar://13611297 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179425 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Revert r179420 and r179421.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179422 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12[mips] Instruction selection patterns for carry-setting and using addAkira Hatanaka
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12[mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179420 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12[ms-inline asm] Move this logic into a static function as it's only applicableChad Rosier
when parsing MS-style inline assembly. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179407 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12[ms-inline asm] Address the FIXME for ImmDisp before brackets. ThisChad Rosier
is a follow on to r179393 and r179399. Test case to be added on the clang side. Part of rdar://13453209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179403 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12[ms-inline asm] Have the [ Symbol ] case fall into the more general logic. ThisChad Rosier
is a follow on to r179393. Test case to be added on the clang side. Part of rdar://13453209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179399 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12ARM: Correct printing of pre-indexed operands.Quentin Colombet
According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179398 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12[ms-inline asm] Add support for operands that include both a symbol and anChad Rosier
immediate displacement. Specifically, add support for generating the proper IR. We've been able to parse this for some time now. Test case to be added on the clang side. Part of rdar://13453209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179393 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12PPC: Remove (broken) nested implicit definition listsHal Finkel
TableGen will not combine nested list 'let' bindings into a single list, and instead uses only the inner scope. As a result, several instruction definitions were missing implicit register defs that were in outer scopes. This de-nests these scopes and makes all instructions have only one let binding which sets implicit register definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179392 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Add a comment about the PPC Interpretation64Bit bitHal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179391 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Hexagon: Set isPredicatedNew flag on predicate new instructions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179388 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Hexagon: Set isPredicatedFlase flag for all the instructions with negated ↵Jyotsna Verma
predication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179387 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-12Add PPC instruction record forms and associated query functionsHal Finkel
This is prep. work for the implementation of optimizeCompare. Many PPC instructions have 'record' forms (in almost all cases, this means that the RC bit is set) that cause the result of the instruction to be compared with zero, and the result of that comparison saved in a predefined condition register. In order to add the record forms of the instructions without too much copy-and-paste, the relevant functions have been refactored into multiclasses which define both the record and normal forms. Also, two TableGen-generated mapping functions have been added which allow querying the instruction code for the record form given the normal form (and vice versa). No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179356 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11[ms-inline asm] Add support for using the LENGTH, TYPE, and SIZE operators withChad Rosier
variables that use namespace alias qualifiers. Test case coming on clang side shortly. Part of rdar://13499009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11[ms-inline asm] Add support for using offsetof operator with variables that useChad Rosier
namespace alias qualifiers. Test case coming on clang side shortly. Part of rdar://13499009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179339 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11[ms-inline asm] Pass a StringRef reference to ParseIntelVarWithQualifier so weChad Rosier
can build up the identifier string. No test case as support for looking up these type of identifiers hasn't been implemented on the clang side. Part of rdar://13499009 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179336 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11[ms-inline asm] Remove brackets from around a symbol reference in the targetChad Rosier
specific logic. This makes the code much less fragile. Test case coming on the clang side in a moment. rdar://13634327 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179323 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11Fix undefined behavior in AArch64David Majnemer
A64Imms::isLogicalImmBits and A64Imms::isLogicalImm will attempt to execute shifts that perform undefined behavior. Instead of attempting to perform the 64-bit rotation, treat it as a no-op. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179317 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11[mips] Custom-lower i64 MULHS and MULHU nodes. Remove the code which selectsAkira Hatanaka
multiply instructions in MipsSEDAGToDAGISel. This patch was supposed to be part of r178403. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179314 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-11[mips] Clean up MipsISelDAGToDAG.cpp and MipsISelLowering.cpp.Akira Hatanaka
- Rename function. - Pass iterator by value. - Remove header include. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179312 91177308-0d34-0410-b5e6-96231b3b80d8
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