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2012-10-30X86 SSE: update rsqrtss and rcpss to use two source operands andManman Ren
the first source operand is tied to the destination operand. This is to accurately model the corresponding instructions where the upper bits are unmodified. rdar://12558838 PR14221 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30X86 MMX: optimize transfer from mmx to i32Manman Ren
We used to generate a store (movq) + a load. Now we use movd. rdar://9946746 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167056 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30[mips] Allow tail-call optimization for vararg functions and functions whichAkira Hatanaka
use the caller's stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167048 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30Add code for saving formal argument information to MipsFunctionInfo. ThisAkira Hatanaka
information will be used by IsEligibleForTailCallOptimization to determine whether a call can be tail-call optimized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167043 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30Add definition of function MipsTargetLowering::passArgOnStack which emits nodesAkira Hatanaka
for passing a function call argument on a stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30Do not do tail-call optimization if target is mips16.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167039 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30PowerPC: Expand FSRQT for vector typesAdhemerval Zanella
This patch expands FSQRT for floating point vector types when altivec is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167034 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30Enable ELF machine type to be specified explicitly in X86 backendMichael Liao
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167027 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30Change ForceSizeOpt attribute into MinSize attributeQuentin Colombet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167020 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30PowerPC: More support for Altivec compare operationsAdhemerval Zanella
This patch adds more support for vector type comparisons using altivec. It adds correct support for v16i8, v8i16, v4i32, and v4f32 vector types for comparison operators ==, !=, >, >=, <, and <=. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167015 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30Use TargetTransformInfo to control switch-to-lookup table transformationHans Wennborg
When the switch-to-lookup tables transform landed in SimplifyCFG, it was pointed out that this could be inappropriate for some targets. Since there was no way at the time for the pass to know anything about the target, an awkward reverse-transform was added in CodeGenPrepare that turned lookup tables back into switches for some targets. This patch uses the new TargetTransformInfo to determine if a switch should be transformed, and removes CodeGenPrepare::ConvertLoadToSwitch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167011 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30Remove an invalid assert in TargetTransformImplHal Finkel
getCastInstrCost had an assert prohibiting scalar to vector casts. Such casts, however, are allowed. This should make the vectorizer buildbot happier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166998 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30ARM: Better disassembly for pc-relative LDR.Jim Grosbach
When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166991 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30Change mips16 delay slot jumps to non delay slot forms by default.Reed Kotler
We will make them delay slot forms if there is something that can be placed in the delay slot during a separate pass. Mips16 extended instructions cannot be placed in delay slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166990 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-30Re-commit r166971. I reverted it to quickly, when buildbots didn't have a chanceJakub Staszak
to test it with chapni's fix (-mattr=+avx). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166985 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby
is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Revert r166971. It causes buildbot failure. To be investigated.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166979 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Remove unused variable.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166973 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Simplify code. No functionality change.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166972 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Allow to fold vector load if there is more than one bitcast, so in the case:Jakub Staszak
%0 = load <8 x i16>* %dest %1 = shufflevector <8 x i16> %0, <8 x i16> %in, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 13, i32 undef, i32 14, i32 14> store <8 x i16> %1, <8 x i16>* %dest We get: vmovlpd (%eax), %xmm0, %xmm0 instead of: vmovaps (%eax), %xmm1 vmovsd %xmm1, %xmm0, %xmm0 No extra test-case is added. I just fixed the existing one (also it uses FileCheck now). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166971 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29This patch solves a problem with passing varargs parameters under the PPC64Bill Schmidt
ELF ABI. A varargs parameter consisting of a single-precision floating-point value, or of a single-element aggregate containing a single-precision floating-point value, must be passed in the low-order (rightmost) four bytes of the doubleword stack slot reserved for that parameter. If there are GPR protocol registers remaining, the parameter must also be mirrored in the low-order four bytes of the reserved GPR. Prior to this patch, such parameters were being passed in the high-order four bytes of the stack slot and the mirrored GPR. The patch adds a new test case to verify the correct code generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166968 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Implement patterns for extloadi8 and extloadi16Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29[ms-inline asm] Add support for the [] operator. Essentially, [expr1][expr2] isChad Rosier
equivalent to [expr1 + expr2]. See test cases for more examples. rdar://12470392 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166949 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Fix PR14204Michael Liao
- Add missing pattern on X86ISD::VZEXT from VR256 to VR256 when AVX2 is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166947 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Fix typoJoerg Sonnenberger
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Allow i32/i64 for 'f' constraint on PowerPC.Ulrich Weigand
This fixes PR12757. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166943 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Minor style fixes for TargetTransformationInfo and TargetTransformImplHans Wennborg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Expand all atomic ops for mips16.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166935 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29PPCSubtarget.h: Add explicit braces.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166932 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29PPCSubtarget.h: Whitespace.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166931 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29This patch adds alignment information for long double to the 64-bit PowerPCBill Schmidt
ELF subtarget. The existing logic is used as a fallback to avoid any changes to the Darwin ABI. PPC64 ELF now has two possible data layout strings: one for FreeBSD, which requires 8-byte alignment, and a default string that requires 16-byte alignment. I've added a test for PPC64 Linux to verify the 16-byte alignment. If somebody wants to add a separate test for FreeBSD, that would be great. Note that there is a companion patch to update the alignment information in Clang, which I am committing now as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166928 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Silence a GCC warning about comparing signed and unsigned types.Duncan Sands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-29Calling TLI->getNumRegisters creates a circular dependency when building ↵Nadav Rotem
LLVM using cmake. Get the number of registers by calling getTypeLegalizationCost. PR14199. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166911 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28Implement brind operator for mips16.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166903 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28Remove TargetELFWriterInfo.Rafael Espindola
All the credit goes to Jan Voung for noticing it was dead! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-28This patch is for the implementation of mips16 complex pattern addr16.Reed Kotler
Previously mips16 was sharing the pattern addr which is used for mips32 and mips64. This had a number of problems: 1) Storing and loading byte and halfword quantities for mips16 has particular problems due to the primarily non mips16 nature of SP. When we must load/store byte/halfword stack objects in a function, we must create a mips16 alias register for SP. This functionality is tested in stchar.ll. 2) We need to have an FP register under certain conditions (such as dynamically sized alloca). We use mips16 register S0 for this purpose. In this case, we also use this register when accessing frame objects so this issue also affects the complex pattern addr16. This functionality is tested in alloca16.ll. The Mips16InstrInfo.td has been updated to use addr16 instead of addr. The complex pattern C++ function for addr has been copied to addr16 and updated to reflect the above issues. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27[code size][ARM] Emit regular call instructions instead of the move, branch ↵Quentin Colombet
sequence git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166854 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27Implement MipsHi for mips16Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166852 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27[mips] Do not tail-call optimize vararg functions or functions with byvalAkira Hatanaka
arguments. This is rather conservative and should be fixed later to be more aggressive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166851 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27[mips] Make sure FuncArg doesn't advance when OrigArgIndex is the same as in theAkira Hatanaka
previous iteration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166850 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27Use the methods and classes that were added to simplify LowerCall and Akira Hatanaka
LowerFormalArguments in MipsTargetLowering. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166846 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27Add method MipsTargetLowering::writeVarArgRegs which copies argument registersAkira Hatanaka
of vararg functions back to the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27Add method MipsTargetLowering::passByValArg.Akira Hatanaka
This method emits nodes for passing byval arguments in registers and stack. This has the same functionality as existing functions PassByValArg64 and WriteByValArg which will be deleted later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-27Add method MipsTargetLowering::copyByValRegs.Akira Hatanaka
This method copies byval arguments passed in registers onto the stack and has the same functionality as existing functions CopyMips64ByValRegs and ReadByValArg which will be deleted later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166841 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Add class MipsCC which provides methods used to analyze formal and callAkira Hatanaka
arguments and inquire about calling convention information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Delete MipsFunctionInfo::InArgFIRange. Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Refactor the VectorTargetTransformInfo interface.Nadav Rotem
Add getCostXXX calls for different families of opcodes, such as casts, arithmetic, cmp, etc. Port the LoopVectorizer to the new API. The LoopVectorizer now finds instructions which will remain uniform after vectorization. It uses this information when calculating the cost of these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166836 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Revert r163298 "Optimize codegen for VSETLNi{8,16,32} operating on Q registers."Jakob Stoklund Olesen
Keep the integer_insertelement test case, the new coalescer can handle this kind of lane insertion without help from pseudo-instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166835 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26Avoid an unused-variable warning when asserts are disabled.Kaelyn Uhrain
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166834 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-26implement mips16 tls global addrReed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166827 91177308-0d34-0410-b5e6-96231b3b80d8
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