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2012-11-15Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missingEli Friedman
case to vector legalization so this actually works. Patch by Pete Couperus. Fixes PR12540. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168107 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15[mips] Add predicate HasFPIdx for floating-point indexed load instructionAkira Hatanaka
support and use it in place of HasMips32r2Or64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15PowerPC: Lowering floor intrinsic for AltivecAdhemerval Zanella
This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and llvm.nearbyint to Altivec instruction when using 4 single-precision float vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Add assertions in MipsLongBranch which check the size of basic blocks.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Return 0 instead of false.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168076 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Simplify code.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Use empty parens for empty function parameter list instead of '(void)'.Dmitri Gribenko
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Revert changing FNEG of v4f32 to Expand. It's legal.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168030 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Make FNEG and FABS of v4f32 Expand.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168029 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Make a bunch of floating point operations on vectors Expand so that ↵Craig Topper
instruction selection won't fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168028 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168025 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Remove unneeded #includes.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168006 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14NVPTXISelLowering.cpp: Fix warnings. [-Wunused-variable]NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Remove the CellSPU port.Eric Christopher
Approved by Chris Lattner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Fix invalid asserts, use llvm_unreachable instead.Jakub Staszak
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167976 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Added multiclass for post-increment load instructions.Jyotsna Verma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167974 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14X86: Enable SSE memory intrinsics even when stack alignment is less than 16 ↵Benjamin Kramer
bytes. The stack realignment code was fixed to work when there is stack realignment and a dynamic alloca is present so this shouldn't cause correctness issues anymore. Note that this also enables generation of AVX instructions for memset under the assumptions: - Unaligned loads/stores are always fast on CPUs supporting AVX - AVX is not slower than SSE We may need some tweaked heuristics if one of those assumptions turns out not to be true. Effectively reverts r58317. Part of PR2962. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167967 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14The code pattern "imm0_255_neg" is used for checking if an immediate value ↵Nadav Rotem
is a small negative number. This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag. rdar://12028498 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167963 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14[NVPTX] Implement custom lowering of loads/stores for i1Justin Holewinski
Loads from i1 become loads from i8 followed by trunc Stores to i1 become zext to i8 followed by store to i8 Fixes PR13291 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167948 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.Jim Grosbach
When an instruction as written requires 32-bit mode and we're assembling in 64-bit mode, or vice-versa, issue a more specific diagnostic about what's wrong. rdar://12700702 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167937 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Set FFLOOR of vectors to expand to keep intruction selection from failing.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Factor out an overly replicated typecast. No functional change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167916 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Set FFLOOR for vectors to expand on CellSPU to keep instruction selection ↵Craig Topper
from failing on llvm.floor of a vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167914 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-14Use TARGET2 relocation for TType references on ARM.Anton Korobeynikov
Do some cleanup of the code while here. Inspired by patch by Logan Chien! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Add (some) PowerPC TLS relocation types to ELF.h andUlrich Weigand
generate them from PPCELFObjectWriter::getRelocTypeInner as appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167864 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Fix wrong PowerPC instruction opcodes for:Ulrich Weigand
- lwaux - lhzux - stbu git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167863 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Fix wrong PowerPC instruction encodings due toUlrich Weigand
operand field name mismatches in: - AForm_3 (fmul, fmuls) - XFXForm_5 (mtcrf) - XFLForm (mtfsf) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167862 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Fix instruction encoding for "bd(n)z" on PowerPC,Ulrich Weigand
by using a new instruction format BForm_1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Fix instruction encoding for "isel" on PowerPC,Ulrich Weigand
using a new instruction format AForm_4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167860 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13X86: when constructing VZEXT_LOAD from other loads, makes sure its outputManman Ren
chain is correctly setup. As an example, if the original load must happen before later stores, we need to make sure the constructed VZEXT_LOAD is constrained to be before the stores. rdar://12684358 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167859 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13misched: Allow subtargets to enable misched and dependent options.Andrew Trick
This allows me to begin enabling (or backing out) misched by default for one subtarget at a time. To run misched we typically want to: - Disable SelectionDAG scheduling (use the source order scheduler) - Enable more aggressive coalescing (until we decide to always run the coalescer this way) - Enable MachineScheduler pass itself. Disabling PostRA sched may follow for some subtargets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167826 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Test commit.Jyotsna Verma
Add a blank line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167819 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12misched: Target-independent support for load/store clustering.Andrew Trick
This infrastructure is generally useful for any target that wants to strongly prefer two instructions to be adjacent after scheduling. A following checkin will add target-specific hooks with unit tests. Then this feature will be enabled by default with misched. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167742 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12Make TOC order deterministic by using MapVector instead of DenseMap.Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167737 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12Remove unused field.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167719 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12Fix PR14314Michael Liao
- Fix operand order for atomic sub, where the minuend is the value loaded from memory and the subtrahend is the parameter specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-12[NVPTX] Add more precise PTX/SM target attributesJustin Holewinski
Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally, PTX 3.1 is added as the default PTX version to be out-of-the-box compatible with CUDA 5.0. Available CPUs for this target: sm_10 - Select the sm_10 processor. sm_11 - Select the sm_11 processor. sm_12 - Select the sm_12 processor. sm_13 - Select the sm_13 processor. sm_20 - Select the sm_20 processor. sm_21 - Select the sm_21 processor. sm_30 - Select the sm_30 processor. sm_35 - Select the sm_35 processor. Available features for this target: ptx30 - Use PTX version 3.0. ptx31 - Use PTX version 3.1. sm_10 - Target SM 1.0. sm_11 - Target SM 1.1. sm_12 - Target SM 1.2. sm_13 - Target SM 1.3. sm_20 - Target SM 2.0. sm_21 - Target SM 2.1. sm_30 - Target SM 3.0. sm_35 - Target SM 3.5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167699 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-11Move some helper methods to being static functions in the implementation file.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-11Use the isTruncFree and isZExtFree API to figure out of these operations are ↵Nadav Rotem
free. Thanks Andy! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10Remove unnecessary subtraction and addition by 1 around a couple for loops.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167673 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10Tidy up spacing. No functional change.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167671 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10Removed unimplemented method declaration.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167670 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10Simplify custom emitter code for pcmp(e/i)str(i/m) and make the helper ↵Craig Topper
functions static. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167669 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10Add more functions to the target library information.Meador Inge
In the process of migrating optimizations from the simplify-libcalls pass to the instcombine pass I noticed that a few functions are missing from the target library information. These functions need to be available for querying in the instcombine library call simplifiers. More functions will probably be added in the future as more simplifiers are migrated to instcombine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10Disable the Thumb no-return call optimization:Evan Cheng
mov lr, pc b.w _foo The "mov" instruction doesn't set bit zero to one, it's putting incorrect value in lr. It messes up backtraces. rdar://12663632 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-10Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167652 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09[NVPTX] Use ABI alignment for parameters when alignment is not specified.Justin Holewinski
Affects SM 2.0+. Fixes bug 13324. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167646 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Add ARM TARGET2 relocation. The testcase will follow with actualy use-case.Anton Korobeynikov
Based on the patch by Logan Chien! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167633 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Switch FreeBSD/i386 back to 4byte stack alignment. This partiallyRoman Divacky
reverts r126226. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167632 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-09Revert r167620; this can be implemented using an existing CL option.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167622 91177308-0d34-0410-b5e6-96231b3b80d8
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