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2012-12-20Undefine PPC harder.Rafael Espindola
This was causing a build failure while trying to build on ppc ubuntu 12.10 with cmake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170668 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20This assert is overly restrictive and does not work for mips16.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170667 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Turn on register scavenger for Mips 16Reed Kotler
We use an unused Mips 32 register for the emergency slot instead of using the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170665 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Refactor SLT (set on less than) instructions. Separate encodingAkira Hatanaka
information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Refactor unconditional branch instruction. Separate encoding informationAkira Hatanaka
from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170663 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass Akira Hatanaka
parameter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170661 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Delete definition of CPRESTORE instruction.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170660 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Refactor conditional branch instructions with one register operand.Akira Hatanaka
Separate encoding information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Refactor conditional branch instructions with two register operands.Akira Hatanaka
Separate encoding information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20fix most of remaining issues with large frames.Reed Kotler
these patches are tested a lot by test-suite but make check tests are forthcoming once the next few patches that complete this are committed. with the next few patches the pass rate for mips16 is near 100% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170656 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copyAkira Hatanaka
physical register $r1 to $r0. GNU disassembler recognizes an "or" instruction as a "move", and this change makes the disassembled code easier to read. Original patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170655 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Fix use-before-construction of X86TargetLowering.Richard Smith
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170654 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Change the order of template parameters. Move the default parameters toAkira Hatanaka
the end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170651 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Refactor shift instructions with register operands. Separate encodingAkira Hatanaka
information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170650 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Refactor shift immediate instructions. Separate encoding informationAkira Hatanaka
from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170649 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Refactor arithmetic and logic instructions with immediate operands.Akira Hatanaka
Separate encoding information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170648 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Refactor arithmetic and logic instructions. Separate encodingAkira Hatanaka
information from the rest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170647 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20[mips] Delete ArithOverflowR and ArithOverflow and use ArithLogicR andAkira Hatanaka
ArithLogicI as the instruction base classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170642 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-20Target/R600: Update MIB according to r170588.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170620 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19MC: Add MCInstrDesc::mayAffectControlFlow() method.Jim Grosbach
MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19R600: Remove unecessary VREG alignment.Tom Stellard
Unlike SGPRs VGPRs doesn't need to be aligned. Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170593 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19R600: control flow optimizationTom Stellard
Branch if we have enough instructions so that it makes sense. Also remove branches if they don't make sense. Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170592 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19R600: New control flow for SI v2Tom Stellard
This patch replaces the control flow handling with a new pass which structurize the graph before transforming it to machine instruction. This has a couple of different advantages and currently fixes 20 piglit tests without a single regression. It is now a general purpose transformation that could be not only be used for SI/R6xx, but also for other hardware implementations that use a form of structurized control flow. v2: further cleanup, fixes and documentation Patch by: Christian König Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Remove the explicit MachineInstrBuilder(MI) constructor.Jakob Stoklund Olesen
Use the version that also takes an MF reference instead. It would technically be possible to extract an MF reference from the MI as MI->getParent()->getParent(), but that would not work for MIs that are not inserted into any basic block. Given the reasonably small number of places this constructor was used at all, I preferred the compile time check to a run time assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170588 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19LLVM sdisel normalize bit extraction of the form:Evan Cheng
((x & 0xff00) >> 8) << 2 to (x >> 6) & 0x3fc This is general goodness since it folds a left shift into the mask. However, the trailing zeros in the mask prevents the ARM backend from using the bit extraction instructions. And worse since the mask materialization may require an addition instruction. This comes up fairly frequently when the result of the bit twiddling is used as memory address. e.g. = ptr[(x & 0xFF0000) >> 16] We want to generate: ubfx r3, r1, #16, #8 ldr.w r3, [r0, r3, lsl #2] vs. mov.w r9, #1020 and.w r2, r9, r1, lsr #14 ldr r2, [r0, r2] Add a late ARM specific isel optimization to ARMDAGToDAGISel::PreprocessISelDAG(). It folds the left shift to the 'base + offset' address computation; change the mask to one which doesn't have trailing zeros and enable the use of ubfx. Note the optimization has to be done late since it's target specific and we don't want to change the DAG normalization. It's also fairly restrictive as shifter operands are not always free. It's only done for lsh 1 / 2. It's known to be free on some cpus and they are most common for address computation. This is a slight win for blowfish, rijndael, etc. rdar://12870177 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170581 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Transform (x&C)>V into (x&C)!=0 where possiblePaul Redmond
When the least bit of C is greater than V, (x&C) must be greater than V if it is not zero, so the comparison can be simplified. Although this was suggested in Target/X86/README.txt, it benefits any architecture with a directly testable form of AND. Patch by Kevin Schoedel git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170576 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19PowerPC: Expand VSELECT nodes.Benjamin Kramer
There's probably a better expansion for those nodes than the default for altivec, but this is better than crashing. VSELECTs occur in loop vectorizer output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund
MVTs, instead of EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund
EVTs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170535 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund
of EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170532 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19X86ISelLowering.cpp: Fix warnings. [-Wlogical-op-parentheses]NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170523 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Optimized load + SIGN_EXTEND patterns in the X86 backend.Elena Demikhovsky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170506 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling
single attribute in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-19Add some missing Defs and Uses.Reed Kotler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170493 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-18Reverse order of checking SSE level when calculating compare cost, so we checkJakub Staszak
AVX2 before AVX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170464 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-18Disable ARM partial flag dependency optimization at -OzQuentin Colombet
To not over constrain the scheduler for ARM in thumb mode, some optimizations for code size reduction, specific to ARM thumb, are blocked when they add a dependency (like write after read dependency). Disables this check when code size is the priority, i.e., code is compiled with -Oz. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170462 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-18Get rid of the pesky -Woverloaded-virtual warning. No change in functionality.Eli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170438 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-18Repair bundles that were broken by removing and reinserting the firstJakob Stoklund Olesen
instruction. This isn't strictly necessary at the moment because Thumb2SizeReduction also copies all MI flags from the old instruction to the new. However, a future patch will make that kind of direct flag tampering illegal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170395 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-18Extract a method, no functional change intended.Jakob Stoklund Olesen
Sadly, this costs us a perfectly good opportunity to use 'goto'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170385 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17[arm fast-isel] Minor cleanup. No functional change intended.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170379 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17[arm fast-isel] Fast-isel only handles simple VTs, so make sure the necessaryChad Rosier
checks are in place. Some minor cleanup as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170360 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add instruction encodings / disassembly support for l2r instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17R600: enable S_*N2_* instructionsTom Stellard
They seem to work fine. Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170343 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17R600: BB operand support for SITom Stellard
Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170342 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17R600: remove nonsense setPrefLoopAlignmentTom Stellard
The Align parameter is a power of two, so 16 results in 64K alignment. Additional to that even 16 byte alignment doesn't make any sense, so just remove it. Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170341 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Revert/correct some FastISel changes in r170104 (EVT->MVT forPatrik Hagglund
TargetLowering::getRegClassFor). Some isSimple() guards were missing, or getSimpleVT() were hoisted too far, resulting in asserts on valid LLVM assembly input. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170336 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add instruction encodings for PEEK and ENDIN.Richard Osborne
Previously these were marked with the wrong format. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Fix parameter name in prototypes in XCoreDisassembler.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170332 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-17Add instruction encodings / disassembly support for rus instructions.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
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