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2012-08-30PPCISelLowering.cpp: Fix r162725.NAKAMURA Takumi
2012-08-30PPCISelLowering.cpp: Whitespace.NAKAMURA Takumi
2012-08-30Add support for moving pure S-register to NEON pipeline if desiredTim Northover
2012-08-30Only perform DAG combine on FMAs of legal types.Craig Topper
2012-08-30Fix PR13727Michael Liao
2012-08-29Rename hasVolatileMemoryRef() to hasOrderedMemoryRef().Jakob Stoklund Olesen
2012-08-29Reserve space for the mandatory traceback fields on PPC64.Hal Finkel
2012-08-29Refactor setExecutionDomain to be clearer about what it's doing and more robust.Tim Northover
2012-08-29Make helper function static.Benjamin Kramer
2012-08-29Make MemoryBuiltins aware of TargetLibraryInfo.Benjamin Kramer
2012-08-29Convert FMA4 patterns to use target specific nodes instead of intrinsics to a...Craig Topper
2012-08-29Cleanup sloppy code. Jakob's review.Andrew Trick
2012-08-29[arm-fast-isel] Add support for ARM PIC.Jush Lu
2012-08-29Fix ARM vector copies of overlapping register tuples.Andrew Trick
2012-08-29cleanupAndrew Trick
2012-08-28Typo.Chad Rosier
2012-08-28Add comments on the literal value used.Michael Liao
2012-08-28The instruction DEXT may be transformed into DEXTU or DEXTM dependingJack Carter
2012-08-28Explicitly update the number of nodes to be traversedMichael Liao
2012-08-28Some instructions are passed to the assembler to beJack Carter
2012-08-28Emit word of zeroes after the last instruction as a start of the mandatoryRoman Divacky
2012-08-28Follow-up patch to r162731.Akira Hatanaka
2012-08-28Add PPC Freescale e500mc and e5500 subtargets.Hal Finkel
2012-08-28The commutative flag is already correctly set within the multiclass. If we setBill Wendling
2012-08-28Convert V_SETALLONES/AVX_SETALLONES/AVX2_SETALLONES to Post-RA pseudos.Craig Topper
2012-08-28Merge AVX_SET0PSY/AVX_SET0PDY/AVX2_SET0 into a single post-RA pseudo.Craig Topper
2012-08-28Fix PR12312Michael Liao
2012-08-28Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ...Jakob Stoklund Olesen
2012-08-28Fix mips' long branch pass.Akira Hatanaka
2012-08-28Split several PPC instruction classes.Hal Finkel
2012-08-28Allow remat of LI on PPC.Hal Finkel
2012-08-28Eliminate redundant CR moves on PPC32.Hal Finkel
2012-08-28Optimize zext on PPC64.Hal Finkel
2012-08-28More missing mayLoad flags on AVX multiclasses.Jakob Stoklund Olesen
2012-08-27Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen
2012-08-27Make sure we add the predicate after all of the registers are added.Bill Wendling
2012-08-27Remove MMX shift intrinsic handling code that also exists in SelectionDAGBuil...Craig Topper
2012-08-27Don't allow vextractf128 to be folded with unaligned stores. We don't fold un...Craig Topper
2012-08-27Fold some patterns into instruction definitons so tablegen can infer flags re...Craig Topper
2012-08-27Add HasAVX1Only predicate and use it for patterns that have an AVX1 instructi...Craig Topper
2012-08-24Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith
2012-08-24Add missing mayLoad flags to a large class of AVX *_Int instructions.Jakob Stoklund Olesen
2012-08-24Missed tLEApcrelJT.Jakob Stoklund Olesen
2012-08-24Explicitly mark LEApcrel pseudos with hasSideEffects.Jakob Stoklund Olesen
2012-08-24Fix call instruction operands in ARMFastISel.Jakob Stoklund Olesen
2012-08-24Mark X86::RET and RETI instructions as variadic.Jakob Stoklund Olesen
2012-08-24Disable Mips' delay slot filler when optimization level is O0.Akira Hatanaka
2012-08-24In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if itsAkira Hatanaka
2012-08-24Lower constant pools and jump tables via TOC on PPC64/SVR4.Roman Divacky
2012-08-24Fix load/store SDNode flags.Jakob Stoklund Olesen
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