aboutsummaryrefslogtreecommitdiff
path: root/lib/Target
AgeCommit message (Expand)Author
2013-03-28Hexagon: Use multiclass for gp-relative instructions.Jyotsna Verma
2013-03-28AArch64: implement GICv3 system registersTim Northover
2013-03-28Add the PPC64 popcntd instructionHal Finkel
2013-03-28Cleanup PPC CR-spill kill flags and 32- vs. 64-bit instructionsHal Finkel
2013-03-28Fix typo in PPCInstr64BitHal Finkel
2013-03-27This patch follows is a follow up to r178171, which uses the register Preston Gurd
2013-03-27[ms-inline asm] Add support of imm displacement before bracketed memoryChad Rosier
2013-03-27Resynchronize isLoadFromStackSlot with LoadRegFromStackSlot (and stores) in P...Hal Finkel
2013-03-27For the current Atom processor, the fastest way to handle a callPreston Gurd
2013-03-27Fix typo (common to both X86 and PPC)Hal Finkel
2013-03-27Remove more dead LR-as-GPR PPC codeHal Finkel
2013-03-27Remove "gpr0 allocation" from the PPC README TODO listHal Finkel
2013-03-27R600/SI: add SETO/SETUO patternsChristian Konig
2013-03-27Print PPC ZERO as 0 (not r0) even on DarwinHal Finkel
2013-03-27Switch to LLVM support function abs64 to keep VS2008 happy.Tim Northover
2013-03-27Enabling the generation of dependency breakers for partial updates on Cortex-...Silviu Baranga
2013-03-27Hexagon: Disable optimizations at O0.Jyotsna Verma
2013-03-27R600/SI: add cummuting of rev instructionsChristian Konig
2013-03-27R600/SI: add mulhu/mulhs patternsChristian Konig
2013-03-27R600/SI: add srl/sha patterns for SIChristian Konig
2013-03-27Allocate r0 on PPCHal Finkel
2013-03-27Use the PPC no-r0 class on the TOC LD pseudosHal Finkel
2013-03-27Apply the no-r0 register class to the PPC SELECT_CC_I[4|8] pseudosHal Finkel
2013-03-27Apply the no-r0 class to PPC TOC ADDI[S] pseudo instructionsHal Finkel
2013-03-27Remove the link register from the GPR classes on PowerPC.Bill Schmidt
2013-03-27Don't spill PPC VRSAVE on non-Darwin (even in SjLj)Hal Finkel
2013-03-26Add XTEST codegen supportMichael Liao
2013-03-26Add HLE target featureMichael Liao
2013-03-26Enable SandyBridgeModel for all modern Intel P6 descendants.Jakob Stoklund Olesen
2013-03-26Restore real bit lengths on PPC register numbersHal Finkel
2013-03-26PPC: Use HWEncoding and TRI->getEncodingValueHal Finkel
2013-03-26R600/SIMCCodeEmitter.cpp: Prune a couple of unused members, STI and Ctx. [-Wu...NAKAMURA Takumi
2013-03-26Use multiple virtual registers in PPC CR spillingHal Finkel
2013-03-26Update PPCRegisterInfo's use of virtual registers to be SSAHal Finkel
2013-03-26Annotate the remaining x86 instructions with SchedRW lists.Jakob Stoklund Olesen
2013-03-26Annotate x87 and mmx instructions with SchedRW lists.Jakob Stoklund Olesen
2013-03-26Annotate control instructions with SchedRW lists.Jakob Stoklund Olesen
2013-03-26Annotate the rest of X86InstrInfo.td with SchedRW lists.Jakob Stoklund Olesen
2013-03-26Add PREFETCHW codegen supportMichael Liao
2013-03-26Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.Jyotsna Verma
2013-03-26Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/...Jyotsna Verma
2013-03-26Revert ARM Scheduler Model: Add resources instructions, map resourcesArnold Schwaighofer
2013-03-26Remove default case from fully covered switch.Benjamin Kramer
2013-03-26R600/SI: improve post ISel foldingChristian Konig
2013-03-26R600/SI: improve vector interpolationChristian Konig
2013-03-26R600/SI: avoid unecessary subreg extraction in IMAGE_SAMPLEChristian Konig
2013-03-26R600/SI: switch back to RegPressure schedulingChristian Konig
2013-03-26R600/SI: mark most intrinsics as readnone v2Christian Konig
2013-03-26R600/SI: replace WQM intrinsicChristian Konig
2013-03-26R600/SI: fix ELSE pseudo op handlingChristian Konig
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-11-25 14:44:32 +0000