llvm - http://llvm.org

Age	Commit message (Expand)	Author
2013-02-17	[XCore] Add missing 2r instructions.	Richard Osborne
2013-02-17	[XCore] Add TSETR instruction.	Richard Osborne
2013-01-25	Add instruction encodings / disassembly support for l4r instructions.	Richard Osborne
2013-01-25	Add instruction encodings / disassembly support for l5r instructions.	Richard Osborne
2013-01-23	Add instruction encodings / disassembly support for l6r instructions.	Richard Osborne
2013-01-22	Add instruction encodings / disassembly support for u10 / lu10 instructions.	Richard Osborne
2013-01-21	Add instruction encodings / disassembly support for u6 / lu6 instructions.	Richard Osborne
2013-01-21	Add instruction encoding / disassembly support for ru6 / lru6 instructions.	Richard Osborne
2013-01-20	Add instruction encodings / disassembly support for l2rus instructions.	Richard Osborne
2013-01-20	Add instruction encodings / disassembly support for l3r instructions.	Richard Osborne
2013-01-20	Add instruction encodings / disassembler support for 2rus instructions.	Richard Osborne
2013-01-20	Add instruction encodings / disassembly support 3r instructions.	Richard Osborne
2012-12-17	Add instruction encodings / disassembly support for l2r instructions.	Richard Osborne
2012-12-17	Add instruction encodings / disassembly support for rus instructions.	Richard Osborne
2012-12-17	Add instruction encodings / disassembly support for 2r instructions.	Richard Osborne
2012-12-17	Add instruction encodings / disassembly support for 0r instructions.	Richard Osborne
2012-12-16	Add instruction encodings and disassembly for 1r instructions.	Richard Osborne
2012-12-16	Remove invalid instruction encodings.	Richard Osborne
2012-12-16	Mark anything deriving from PseudoInstXCore as a pseudo instruction.	Richard Osborne
2012-12-16	Set instruction size correctly in XCoreInstrFormats.td	Richard Osborne
2012-02-18	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...	Jia Liu
2008-11-07	Add XCore backend.	Richard Osborne