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path: root/lib/Target/Sparc/SparcRegisterInfo.cpp
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2013-04-06SPARC v9 stack pointer bias.Jakob Stoklund Olesen
64-bit SPARC v9 processes use biased stack and frame pointers, so the current function's stack frame is located at %sp+BIAS .. %fp+BIAS where BIAS = 2047. This makes more local variables directly accessible via [%fp+simm13] addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178965 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-02Add an I64Regs register class for 64-bit registers.Jakob Stoklund Olesen
We are going to use the same registers for 32-bit and 64-bit values, but in two different register classes. The I64Regs register class has a larger spill size and alignment. The addition of an i64 register class confuses TableGen's type inference, so it is necessary to clarify the type of some immediates and the G0 register. In 64-bit mode, pointers are i64 and should use the I64Regs register class. Implement getPointerRegClass() to dynamically provide the pointer register class depending on the subtarget. Use ptr_rc and iPTR for memory operands. Finally, add the i64 type to the IntRegs register class. This register class is not used to hold i64 values, I64Regs is for that. The type is required to appease TableGen's type checking in output patterns like this: def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>; SPARC v9 uses the same ADDrr instruction for i32 and i64 additions, and TableGen doesn't know to check the type of register sub-classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178522 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-21Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky
to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-31[PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier
Each target implementation was needlessly recomputing the index. Part of rdar://13076458 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-02Move all of the header files which are involved in modelling the LLVM IRChandler Carruth
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-03Use the new script to sort the includes of every file under lib.Chandler Carruth
Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-06Remove empty overrides of processFunctionBeforeFrameFinalized().Roman Divacky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161328 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper
some superfluous forward declarations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper
size of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu
MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20More dead code removal (using -Wunreachable-code)David Blaikie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng
better location welcome). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-18Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng
to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng
registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-28Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134027 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-27Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng
into XXXGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-24Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng
target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-09Remove custom allocation order boilerplate that is no longer needed.Jakob Stoklund Olesen
The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-30Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola
directives. Fixes PR9826. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-18Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-15First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov
out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-26Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach
to try to re-use scavenged frame index reference registers. rdar://8277890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-02cleanupRafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105322 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-02use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09Change the Value argument to eliminateFrameIndex to a type-tagged value. ThisJim Grosbach
is preparatory to having PEI's scavenged frame index value reuse logic properly distinguish types of frame values (e.g., whether the value is stack-pointer relative or frame-pointer relative). No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-12Make the MachineFunction argument of getFrameRegister const.David Greene
This also fixes a build error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87027 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-07Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach
a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-08Add source debug information to the Sparc code generator.Richard Pennington
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81215 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-14llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin
This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-11assert(0) -> LLVM_UNREACHABLE.Torok Edwin
Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-23Propagate debug loc info through prologue/epilogue.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65298 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-13Remove non-DebugLoc versions of buildMI from Sparc.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64435 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-03Switch the MachineOperand accessors back to the short names likeDan Gohman
isReg, etc., from isRegister, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-03Emit saveri with the correct operand order, patch by Richard Pennington!Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54313 91177308-0d34-0410-b5e6-96231b3b80d8
2008-03-31Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-07Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson
Some day I'll get it all moved over... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-31Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson
Machine-level API cleanup instigated by Chris. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-30Add new shorter predicates for testing machine operands for various types: Chris Lattner
e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-30Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner
Likewise setImmedValue -> setImm git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29Remove attribution from file headers, per discussion on llvmdev.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-05Add a argument to storeRegToStackSlot and storeRegToAddr to specify whetherEvan Cheng
the stored register is killed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-02Remove redundant foldMemoryOperand variants and other code clean up.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44517 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-13Add parameter to getDwarfRegNum to permit targetsDale Johannesen
to use different mappings for EH and debug info; no functional change yet. Fix warning in X86CodeEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44056 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-11Use TableGen to emit information for dwarf register numbers. Anton Korobeynikov
This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-18- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but ↵Evan Cheng
only returns the opcode of the instruction post unfolding. - Fix some copy+paste bugs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-18Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister ↵Evan Cheng
public interface. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43150 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-05- Added a few target hooks to generate load / store instructions from / to anyEvan Cheng
address (not just from / to frameindexes). - Added target hooks to unfold load / store instructions / SDNodes into separate load, data processing, store instructions / SDNodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
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