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Age	Commit message (Expand)	Author
2013-05-13	Remove unused fields and arguments.	Rafael Espindola
2013-05-13	Remove the MachineMove class.	Rafael Espindola
2013-05-10	Fix the R600 build.	Rafael Espindola
2013-05-10	R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen ...	Tom Stellard
2013-05-10	R600: Expand SUB for v2i32/v4i32	Tom Stellard
2013-05-10	R600: Expand MUL for v4i32/v2i32	Tom Stellard
2013-05-10	R600: Expand SRA for v4i32/v2i32	Tom Stellard
2013-05-10	R600: Expand vselect for v4i32 and v2i32	Tom Stellard
2013-05-06	R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode	Tom Stellard
2013-05-06	R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemask	Tom Stellard
2013-05-06	R600/SI: Add intrinsic for texture image loading	Tom Stellard
2013-05-06	R600/SI: Add pattern for uint_to_fp	Tom Stellard
2013-05-06	R600/SI: Add patterns for integer maxima / minima	Tom Stellard
2013-05-06	R600/SI: Add pattern for AMDGPU.trunc intrinsic	Tom Stellard
2013-05-06	R600: Remove dead code from the CodeEmitter v2	Tom Stellard
2013-05-06	R600: Emit config values in register / value pairs	Tom Stellard
2013-05-06	R600: Stop emitting the instruction type byte before each instruction	Tom Stellard
2013-05-06	R600: Emit ISA for CALL_FS_* instructions	Tom Stellard
2013-05-03	R600: Expand vector or, shl, srl, and xor nodes	Tom Stellard
2013-05-03	R600: BFI_INT is a vector-only instruction	Tom Stellard
2013-05-03	R600: Add pattern for SHA-256 Ma function	Tom Stellard
2013-05-03	R600: Clean up comments in Processors.td	Tom Stellard
2013-05-02	R600: Signed literals are 64bits wide	Vincent Lejeune
2013-05-02	R600: If previous bundle is dot4, PV valid chan is always X	Vincent Lejeune
2013-05-02	R600: Improve asmPrint of ALU clause	Vincent Lejeune
2013-05-02	R600: Prettier asmPrint of Alu	Vincent Lejeune
2013-05-02	R600: Use new tablegen syntax for patterns	Tom Stellard
2013-05-02	R600/SI: remove nonsense select pattern	Tom Stellard
2013-04-30	R600: Always use texture cache for compute shaders	Vincent Lejeune
2013-04-30	R600: use native for alu	Vincent Lejeune
2013-04-30	R600: Packetize instructions	Vincent Lejeune
2013-04-30	R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips	Vincent Lejeune
2013-04-30	R600: Add a Bank Swizzle operand	Vincent Lejeune
2013-04-30	R600: Take inner dependency into tex/vtx clauses	Vincent Lejeune
2013-04-30	R600: Turn TEX/VTX into native instructions	Vincent Lejeune
2013-04-30	R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions	Vincent Lejeune
2013-04-30	R600: Add some new processor variants	Vincent Lejeune
2013-04-30	R600: Clean up instruction class definitions	Vincent Lejeune
2013-04-30	R600: config section now reports use of killgt	Vincent Lejeune
2013-04-29	R600: Use correct CF_END instruction on Northern Island GPUs	Tom Stellard
2013-04-29	R600: Fix encoding of CF_END_{EG, R600} instructions	Tom Stellard
2013-04-26	R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE	Tom Stellard
2013-04-24	R600: Initialize BooleanVectorContents	Tom Stellard
2013-04-24	R600: Use SHT_PROGBITS for the .AMDGPU.config section	Tom Stellard
2013-04-23	R600: Use .AMDGPU.config section to emit stacksize	Vincent Lejeune
2013-04-23	R600: Add CF_END	Vincent Lejeune
2013-04-22	Remove unused DwarfSectionOffsetDirective string	Matt Arsenault
2013-04-19	ArrayRefize getMachineNode(). No functionality change.	Michael Liao
2013-04-19	R600: Add pattern for the BFI_INT instruction	Tom Stellard
2013-04-19	R600/SI: Use InstFlag for VOP3 modifier operands	Tom Stellard