| Age | Commit message (Expand) | Author |
|---|
| 2013-04-01 | Add more PPC floating-point conversion instructions | Hal Finkel |
| 2013-03-31 | Add the PPC lfiwax instruction | Hal Finkel |
| 2013-03-29 | Add PPC FP rounding instructions fri[mnpz] | Hal Finkel |
| 2013-03-28 | Add the PPC64 ldbrx/stdbrx instructions | Hal Finkel |
| 2013-03-28 | Add the PPC64 popcntd instruction | Hal Finkel |
| 2013-02-01 | Add notes about future PowerPC features | Bill Schmidt |
| 2013-02-01 | LLVM enablement for some older PowerPC CPUs | Bill Schmidt |
| 2013-01-30 | Add definitions for the PPC a2q core marked as having QPX available | Hal Finkel |
| 2012-08-28 | Add PPC Freescale e500mc and e5500 subtargets. | Hal Finkel |
| 2012-06-22 | Add support for the PPC isel instruction. | Hal Finkel |
| 2012-06-12 | Fixes for PPC host detection and features. | Hal Finkel |
| 2012-06-11 | Enable MFOCRF generation on the PPC A2 core. | Hal Finkel |
| 2012-06-11 | Rename the PPC target feature gpul to mfocrf. | Hal Finkel |
| 2012-06-11 | Add POWER6 and POWER7 CPU types to the PPC backend. | Hal Finkel |
| 2012-04-01 | Fix some 80-col. violations I introduced with the A2 PPC64 core. | Hal Finkel |
| 2012-04-01 | Add instruction itinerary for the PPC64 A2 core. | Hal Finkel |
| 2012-02-18 | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu |
| 2011-10-17 | Add PPC 440 scheduler and some associated tests | Hal Finkel |
| 2011-10-14 | initial test commit (remove whitespace) | Hal Finkel |
| 2010-11-15 | dissolve some more hacks. | Chris Lattner |
| 2010-04-05 | Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field. | Jakob Stoklund Olesen |
| 2008-11-24 | Move target independent td files from lib/Target/ to include/llvm/Target so t... | Evan Cheng |
| 2007-12-29 | Remove attribution from file headers, per discussion on llvmdev. | Chris Lattner |
| 2007-03-06 | Switch PPC return lower to use an autogenerated CC description. | Chris Lattner |
| 2006-12-12 | Honor cpu directive, take two. | Jim Laskey |
| 2006-06-16 | Rename some subtarget features. A CPU now can *have* 64-bit instructions, | Chris Lattner |
| 2006-05-18 | getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. | Evan Cheng |
| 2006-05-17 | Remove PointerType from class Target | Evan Cheng |
| 2006-03-16 | add callee saved vector regs | Chris Lattner |
| 2006-03-13 | Mark instructions that are cracked by the PPC970 decoder as such. | Chris Lattner |
| 2006-03-12 | Several big changes: | Chris Lattner |
| 2006-02-28 | Add a subtarget feature for the stfiwx instruction. I know the G5 has it, | Chris Lattner |
| 2006-01-27 | Subtarget feature can now set any variable to any value | Evan Cheng |
| 2005-10-26 | Add attribute name and type to SubtargetFeatures. | Jim Laskey |
| 2005-10-23 | mark this as beta | Chris Lattner |
| 2005-10-23 | rearrange things a bit so that instructions can use subtarget features in the | Chris Lattner |
| 2005-10-23 | improve -help output | Chris Lattner |
| 2005-10-22 | Add g3 back to the mix and reorder to irritate them anal folk. Actually, it's | Jim Laskey |
| 2005-10-21 | 64-bit reg support should not be enabled by default, as support isn't complete. | Chris Lattner |
| 2005-10-21 | Plugin new subtarget backend into the build. | Jim Laskey |
| 2005-10-19 | Added InstrSchedClass to each of the PowerPC Instructions. | Jim Laskey |
| 2005-10-14 | Rename PowerPC*.td -> PPC*.td | Chris Lattner |
| 2005-10-14 | Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td | Chris Lattner |
