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path: root/lib/Target/Mips/MipsSubtarget.cpp
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2013-05-10Checkin in of first of several patches to finish implementation ofReed Kotler
mips16/mips32 floating point interoperability. This patch fixes returns from mips16 functions so that if the function was in fact called by a mips32 hard float routine, then values that would have been returned in floating point registers are so returned. Mips16 mode has no floating point instructions so there is no way to load values into floating point registers. This is needed when returning float, double, single complex, double complex in the Mips ABI. Helper functions in libc for mips16 are available to do this. For efficiency purposes, these helper functions have a different calling convention from normal Mips calls. Registers v0,v1,a0,a1 are used to pass parameters instead of a0,a1,a2,a3. This is because v0,v1,a0,a1 are the natural registers used to return floating point values in soft float. These values can then be moved to the appropriate floating point registers with no extra cost. The only register that is modified is ra in this call. The helper functions make sure that the return values are in the floating point registers that they would be in if soft float was not in effect (which it is for mips16, though the soft float is implemented using a mips32 library that uses hard float). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10This is for an experimental option -mips-os16. The idea is to compile allReed Kotler
Mips32 code as Mips16 unless it can't be compiled as Mips 16. For now this would happen as long as floating point instructions are not needed. Probably it would also make sense to compile as mips32 if atomic operations are needed too. There may be other cases too. A module pass prescans the IR and adds the mips16 or nomips16 attribute to functions depending on the functions needs. Mips 16 mode can result in a 40% code compression by utililizing 16 bit encoding of many instructions. The hope is for this to replace the traditional gcc way of dealing with Mips16 code using floating point which involves essentially using soft float but with a library implemented using mips32 floating point. This gcc method also requires creating stubs so that Mips32 code can interact with these Mips 16 functions that have floating point needs. My conjecture is that in reality this traditional gcc method would never win over this new method. I will be implementing the traditional gcc method also. Some of it is already done but I needed to do the stubs to finish the work and those required this mips16/32 mixed mode capability. I have more ideas for to make this new method much better and I think the old method will just live in llvm for anyone that needs the backward compatibility but I don't for what reason that would be needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179185 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09This patch enables llvm to switch between compiling for mips32/mips64 Reed Kotler
and mips16 on a per function basis. Because this patch is somewhat involved I have provide an overview of the key pieces of it. The patch is written so as to not change the behavior of the non mixed mode. We have tested this a lot but it is something new to switch subtargets so we don't want any chance of regression in the mainline compiler until we have more confidence in this. Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1. For that reason there are derived versions of the register info, frame info, instruction info and instruction selection classes. Now we register three separate passes for instruction selection. One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and MipsSEISelDAGToDAG.cpp). When the ModuleISel pass runs, it determines if there is a need to switch subtargets and if so, the owning pointers in MipsTargetMachine are appropriately changed. When 16Isel or SEIsel is run, they will return immediately without doing any work if the current subtarget mode does not apply to them. In addition, MipsAsmPrinter needs to be reset on a function basis. The pass BasicTargetTransformInfo is substituted with a null pass since the pass is immutable and really needs to be a function pass for it to be used with changing subtargets. This will be fixed in a follow on patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-05[mips] Remove android calling convention.Akira Hatanaka
This calling convention was added just to handle functions which return vector of floats. The fix committed in r165585 solves the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176530 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-05This patch that sets the Mips ELF header flag for Jack Carter
MicroMips architectures. Contributer: Zoran Jovanovic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174360 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-30This patch implements runtime Mips specificJack Carter
setting of ELF header e_flags. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173884 91177308-0d34-0410-b5e6-96231b3b80d8
2012-12-07[mips] Delete unused sub-target features.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-15[mips] Add predicate HasFPIdx for floating-point indexed load instructionAkira Hatanaka
support and use it in place of HasMips32r2Or64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168089 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25Initialize boolean variables in MipsSubtarget's constructor.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164642 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22Add register Mips::GP to the list of reserved registers if target is bare-metalAkira Hatanaka
to prevent it from being clobbered. mips uses $gp to access small data section. This bug was originally reported by Carl Norum. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-14Fix coding style violations. Remove white spaces and tabs.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-16This patch adds the register class for MIPS16 as well as the ability forAkira Hatanaka
llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the mips16 ASE for mips32 by default. As part of fixing of adding this we discovered some small changes that need to be made to MipsInstrInfo::storeRegToStackSLot and MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead, per suggestion of Jakob Stoklund Olesen. Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156958 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-15Temporarily disable anti-dependence breaking for Mips until bug 12829 isAkira Hatanaka
resolved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156801 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Turn off post-RA scheduler by default.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153557 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-28Turn on post register allocation scheduler.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153554 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28remove blanks, and some code formatJia Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-17remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20Unweaken vtables as per ↵David Blaikie
http://llvm.org/docs/CodingStandards.html#ll_virtual_anch git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29Change names for MIPS "generic" processors defined in Mips.td to match what GNUAkira Hatanaka
tools use. Patch by Simon Atanasyan. "mips32r1" => "mips32" "4ke" => mips32r2" "mips64r1" => "mips64" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145451 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21Undo a change made in r140254.Akira Hatanaka
MipsArchVersion needs to be initialized to Mips32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140261 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21MipsArchVersion does not need to be in the initialization list and MipsABIAkira Hatanaka
should be initialized to UnknownABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140254 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-21Set ABI if it hasn't been set on the command line.Akira Hatanaka
Check if architecture & ABI combination is valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140230 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Drop support for Mips1 and Mips2.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Drop support for Allegrex. Allegrex implements a variant of Mips2.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-09Change default target architecture from Mips1 to Mips32r1 in preparation forAkira Hatanaka
removing support for Mips1 and Mips2. This change and the ones that follow have been discussed with and approved by Bruno. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139344 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-24Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng
These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-14Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng
registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-11- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng
and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-09Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng
CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134795 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-08Eliminate asm parser's dependency on TargetMachine:Evan Cheng
- Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-07Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-01- Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng
itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-30Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng
be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15Reverse unnecessary changes made in r129606 and r129608. There is no change ↵Akira Hatanaka
in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15Fix lines that have incorrect indentation or exceed 80 columns. There is no ↵Akira Hatanaka
change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129606 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04Remove (hopefully) all trailing whitespaces from the mips backend. Patch by ↵Bruno Cardoso Lopes
Hatanaka, Akira git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13reintroduce support for Mips "small" section handling. This is Chris Lattner
implemented somewhat differently than before, but it should have the same functionality and the previous testcase passes again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78900 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13Restore some "small section" support code, reverting my patch from r76936.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78894 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-03Remove -disable-mips-abicall and -enable-mips-absolute-call command-line Eli Friedman
options, which don't appear to be useful. -enable-mips-absolute-call is completely unused (and unless I'm mistaken, is supposed to have the same effect that -relocation-model=dynamic-no-pic should have), and -disable-mips-abicall appears to be effectively a synonym for -relocation-model=static. Adjust the few users of hasABICall to checks which seem more appropriate. Update MipsSubtarget, MipsTargetMachine, and MipselTargetMachine to synchronize with recent changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77938 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-02Normalize Subtarget constructors to take a target triple string instead ofDaniel Dunbar
Module*. Also, dropped uses of TargetMachine where unnecessary. The only target which still takes a TargetMachine& is Mips, I would appreciate it if someone would normalize this to match other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-24remove more remnants of small section support.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76936 91177308-0d34-0410-b5e6-96231b3b80d8
2009-05-27Added support for fround, fextend and FP_TO_SINTBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72483 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-15Fixed Bug 2751Bruno Cardoso Lopes
http://llvm.org/bugs/show_bug.cgi?id=2751 Abicall was enabled even when static code model was provided in the command line. The correct behavior is to disable abicall when static is specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56228 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-22Make option variables static, so they won't cause nameclashAnton Korobeynikov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55203 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-13Removed SELECT_CC custom lowering. This is not needed anymore, the SELECT nodeBruno Cardoso Lopes
is lowered properly and covers everything LowerSELECT_CC did. Added method printUnsignedImm in AsmPrinter to print uimm16 operands. This avoid the ugly instruction by instruction checking in printOperand. Added a swap instruction present in the allegrex core. Added two conditional instructions present in the allegrex core : MOVZ and MOVN. They both allow a more efficient SELECT operation for integers. Also added SELECT patterns to optimize MOVZ and MOVN usage. The brcond and setcc patterns were cleaned: redundant and suboptimal patterns were removed. The suboptimals were replaced by more efficient ones. Fixed some instructions that were using immZExt16 instead of immSExt16. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54724 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-08Support added for ctlz intrinsic, test case added.Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54516 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-08Match raw "psp" triple target, as done by the homebrew toolchain.Bruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54514 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-30Added new features to represent specific instructions groupsBruno Cardoso Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54213 91177308-0d34-0410-b5e6-96231b3b80d8
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