| Age | Commit message (Expand) | Author |
|---|
| 2013-05-10 | Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. | Jyotsna Verma |
| 2013-05-07 | Hexagon: Set accessSize and addrMode on all load/store instructions. | Jyotsna Verma |
| 2013-05-06 | Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. | Jyotsna Verma |
| 2013-05-02 | reverting r180953 | Jyotsna Verma |
| 2013-05-02 | Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. | Jyotsna Verma |
| 2013-05-01 | Hexagon: Use multiclass for Jump instructions. | Jyotsna Verma |
| 2013-04-23 | Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. | Jyotsna Verma |
| 2013-04-23 | Hexagon: Define relations for GP-relative instructions. | Jyotsna Verma |
| 2013-04-23 | Hexagon: Remove duplicate instructions to handle global/immediate values | Jyotsna Verma |
| 2013-04-12 | Hexagon: Set isPredicatedNew flag on predicate new instructions. | Jyotsna Verma |
| 2013-04-12 | Hexagon: Set isPredicatedFlase flag for all the instructions with negated pre... | Jyotsna Verma |
| 2013-03-28 | Hexagon: Use multiclass for gp-relative instructions. | Jyotsna Verma |
| 2013-03-26 | Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. | Jyotsna Verma |
| 2013-03-22 | Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and w... | Jyotsna Verma |
| 2013-03-08 | Hexagon: Add patterns for zero extended loads from i1->i64. | Jyotsna Verma |
| 2013-03-07 | Hexagon: Add support to lower block address. | Jyotsna Verma |
| 2013-03-05 | reverting patch 176508. | Jyotsna Verma |
| 2013-03-05 | Hexagon: Add support for lowering block address. | Jyotsna Verma |
| 2013-02-15 | Hexagon: Set appropriate TSFlags to the loads/stores with global address to | Jyotsna Verma |
| 2013-02-14 | Hexagon: Use multiclass for absolute addressing mode loads. | Jyotsna Verma |
| 2013-02-13 | Hexagon: Use absolute addressing mode loads/stores for global+offset | Jyotsna Verma |
| 2013-02-05 | Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle | Jyotsna Verma |
| 2013-02-05 | Hexagon: Use multiclass for absolute addressing mode stores. | Jyotsna Verma |
| 2013-02-05 | Hexagon: Add V4 compare instructions. Enable relationship mapping | Jyotsna Verma |
| 2013-02-04 | Hexagon: Add V4 combine instructions and some more Def Pats for V2. | Jyotsna Verma |
| 2013-02-01 | Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats". | Jyotsna Verma |
| 2013-02-01 | Add appropriate TSFlags to the instructions that must be always extended. | Jyotsna Verma |
| 2013-01-29 | Use multiclass for post-increment store instructions. | Jyotsna Verma |
| 2013-01-29 | Add constant extender support for MInst type instructions. | Jyotsna Verma |
| 2013-01-07 | Remove more unnecessary # operators with nothing to paste proceeding them. | Craig Topper |
| 2013-01-07 | Remove # from the beginning and end of def names. The # is a paste operator a... | Craig Topper |
| 2012-12-20 | Add constant extender support to GP-relative load/store instructions. | Jyotsna Verma |
| 2012-12-20 | Add TSFlags to ALU32 type instructions for constant-extender/Relationship maps. | Jyotsna Verma |
| 2012-12-11 | Use multiclass for new-value store instructions with MEMri operand. | Jyotsna Verma |
| 2012-12-05 | Define new-value store instructions with base+immediate addressing mode | Jyotsna Verma |
| 2012-12-05 | Use multiclass to define store instructions with base+immediate offset | Jyotsna Verma |
| 2012-12-04 | Define store instructions with base+register offset addressing mode | Jyotsna Verma |
| 2012-12-04 | Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading... | Jyotsna Verma |
| 2012-12-03 | Define store instructions with base+immediate offset addressing mode | Jyotsna Verma |
| 2012-11-30 | Use multiclass for the store instructions with MEMri operand. | Jyotsna Verma |
| 2012-11-30 | Use multiclass for the load instructions with 'base + register offset' | Jyotsna Verma |
| 2012-11-20 | Removing some unused instruction definitions from the Hexagon backend. | Jyotsna Verma |
| 2012-11-14 | Added multiclass for post-increment load instructions. | Jyotsna Verma |
| 2012-07-13 | Remove variable_ops from call instructions in most targets. | Jakob Stoklund Olesen |
| 2012-05-14 | Revert 156634 upon request until code improvement changes are made. | Brendon Cahoon |
| 2012-05-11 | Hexagon constant extender support. | Brendon Cahoon |
| 2012-05-08 | Update load/store instruction patterns in Hexagon V4. | Sirish Pande |
| 2012-05-03 | Extensions of Hexagon V4 instructions. | Sirish Pande |
| 2012-04-23 | Revert r155365, r155366, and r155367. All three of these have regression | Chandler Carruth |
| 2012-04-23 | Support for Hexagon VLIW Packetizer. | Sirish Pande |
