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AgeCommit message (Expand)Author
2012-04-30Don't introduce illegal types when creating vmull operations. <rdar://11324364>Bob Wilson
2012-04-28Fix a problem with blocks that need to be split twice.Jakob Stoklund Olesen
2012-04-27ARM: Thumb add(sp plus register) asm constraints.Jim Grosbach
2012-04-27ARM: Tweak tADDrSP definition for consistent operand order.Jim Grosbach
2012-04-27Track worst case alignment padding more accurately.Jakob Stoklund Olesen
2012-04-27Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,Lang Hames
2012-04-27Fix ARM assembly parsing for upper case condition codes on IT instructions.Richard Barton
2012-04-27Refactor IT handling not to store the bottom bit of the condition code in the...Richard Barton
2012-04-27Implement a bastardized ABI.Evan Cheng
2012-04-27- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2Evan Cheng
2012-04-26ARM: Thumb ldr(literal) base address alignment is 32-bits.Jim Grosbach
2012-04-26Use VLD1 in NEON extenting-load patterns instead of VLDR.Tim Northover
2012-04-26Test commit.Tim Northover
2012-04-26If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assumeEvan Cheng
2012-04-25Unify internal representation of ARM instructions with a register right-shift...Richard Barton
2012-04-25Add ifdef around getSubtargetFeatureName in tablegen output file so that only...Craig Topper
2012-04-24ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach
2012-04-24ARM: Nuke remnant bogus code.Jim Grosbach
2012-04-24Refactor Thumb ITState handling in ARM Disassembler to more efficiently use i...Richard Barton
2012-04-23Tidy up. 80 columns, whitespace, et. al.Jim Grosbach
2012-04-23This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd
2012-04-23ARM: VSLI two-operand assmebly aliases are tblgen'erated.Jim Grosbach
2012-04-23ARM: tblgen'erate VSRA/VRSRA/VSRI assembly two-operand aliases.Jim Grosbach
2012-04-23ARM: vqdmulh two-operand aliases are tblgen'erated now.Jim Grosbach
2012-04-22ARM: Initialize the HasRAS bit.Benjamin Kramer
2012-04-20ARM: tblgen'erate more NEON two-operand aliases.Jim Grosbach
2012-04-20ARM: tblgen'erate more NEON two-operand aliases.Jim Grosbach
2012-04-20ARM: Update NEON assembly two-operand aliases.Jim Grosbach
2012-04-20Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change s...Craig Topper
2012-04-20ARM some VFP tblgen'erated two-operand aliases.Jim Grosbach
2012-04-19ARM let TableGen handle a few two-operand aliases.Jim Grosbach
2012-04-18Added support for disassembling unpredictable swp/swpb ARM instructions.Silviu Baranga
2012-04-18Fix the bahavior of the disassembler when decoding unpredictable mrs instruct...Silviu Baranga
2012-04-18Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ...Silviu Baranga
2012-04-18Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocess...Silviu Baranga
2012-04-18Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instruct...Silviu Baranga
2012-04-17Typo.Chad Rosier
2012-04-17Remove unused CCIfSubtarget.Jay Foad
2012-04-17Fix bad EXTRACT_SUBREG in instruction selection for extending-loads on NEON.James Molloy
2012-04-17Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)Kevin Enderby
2012-04-16ARM two-operand forms for vhadd and vhsub instructions.Jim Grosbach
2012-04-16ARM handle :lower16: and :upper16: after a '#' prefix.Jim Grosbach
2012-04-16ARM assembly two-operand forms for VRSHL.Jim Grosbach
2012-04-16ARM two-operand aliases for VRHADD instructions.Jim Grosbach
2012-04-15Wire up support for diagnostic ranges in the ARMAsmParser.Benjamin Kramer
2012-04-13On Darwin targets, only use vfma etc. if the source use fma() intrinsic expli...Evan Cheng
2012-04-13For ARM disassembly only print 32 unsigned bits for the address of branchKevin Enderby
2012-04-12Fix a few more places in the ARM disassembler so that branches getKevin Enderby
2012-04-12ARM 'adr' fixups don't need the interworking addend tweaking.Jim Grosbach
2012-04-11Fixed a case of ARM disassembly getting an assert on a bad encodingKevin Enderby
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