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AgeCommit message (Expand)Author
2010-11-29Refactor some of the "disassembly-only" instructions into a base class. ThisBill Wendling
2010-11-29Update fastisel for the changes in r120272.Eric Christopher
2010-11-29Rename t2 TBB and TBH instructions to reference that they encode the jump tableJim Grosbach
2010-11-29Improving the factoring of several instruction encodings.Owen Anderson
2010-11-29Add support for NEON VLD3-dup instructions.Bob Wilson
2010-11-29Fix copy-and-paste errors in VLD2-dup scheduling itineraries.Bob Wilson
2010-11-29ARM Pseudo-ize tBR_JTr.Jim Grosbach
2010-11-29Thumb2 encodings for MSR and MRS.Owen Anderson
2010-11-29Thumb2 encodings for system instructions.Owen Anderson
2010-11-29Thumb2 encodings for branches and IT blocks.Owen Anderson
2010-11-29The ARM BR_JT* pseudos don't need to use the printer jtblock_operand node toJim Grosbach
2010-11-29I swear I did a make clean and make before committing all this...Michael J. Spencer
2010-11-29Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos.Jim Grosbach
2010-11-29Add more Thumb encodings.Bill Wendling
2010-11-29More Thumb encodings.Bill Wendling
2010-11-29Add Thumb encodings for REV instructions.Bill Wendling
2010-11-29Add more Thumb encodings.Bill Wendling
2010-11-28Add support for NEON VLD2-dup instructions.Bob Wilson
2010-11-28Another minor refactoring for VLD1DUP instructions.Bob Wilson
2010-11-28Add entry in getTargetNodeName() for ARMISD::VBICIMM.Bob Wilson
2010-11-27Move more PEI-related hooks to TFIAnton Korobeynikov
2010-11-27Move callee-saved regs spills / reloads to TFIAnton Korobeynikov
2010-11-27Refactor. Set alignment bit in VLD1-dup instruction classes.Bob Wilson
2010-11-27Add NEON VLD1-dup instructions (load 1 element to all lanes).Bob Wilson
2010-11-27Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions.Bob Wilson
2010-11-27MC/Mach-O: Switch to using MachOFormat.h.Daniel Dunbar
2010-11-26Remove the unused TheTarget member.Rafael Espindola
2010-11-23Move the ARM reloc constants to Support/ELF.hJason W Kim
2010-11-23Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.Bob Wilson
2010-11-23Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck
2010-11-22Fix epilogue codegen to avoid leaving the stack pointer in an invalidEvan Cheng
2010-11-22Fix a compiler warning about Kind being used uninitializedDuncan Sands
2010-11-21Pseudos default to 4byte size, let the instruction size field noticeEric Christopher
2010-11-21More Thumb encodings.Bill Wendling
2010-11-21Add encoding for ARM "trap" instruction.Bill Wendling
2010-11-21The "trap" instruction is one of this which doesn't have a condition code. HackBill Wendling
2010-11-21- Give "trap" the correct encoding, at least according to Darwin's assembler.Bill Wendling
2010-11-21Use by-name rather than by-order operand matching for some NEON encodings.Owen Anderson
2010-11-21BR_JTadd is ARM-only, so use the proper pseudo class to get the predicate.Jim Grosbach
2010-11-20A few more thumb instruction MC encodings.Bill Wendling
2010-11-20Rewrite address handling to use a structure with all the possible addressEric Christopher
2010-11-20STRH only needs the additional operand, not t2STRH. Also invert conditionalEric Christopher
2010-11-20Move some more hooks to TargetFrameInfoAnton Korobeynikov
2010-11-20Add more Thumb add instruction encodings.Bill Wendling
2010-11-20Add Thumb encodings for some add instructions.Bill Wendling
2010-11-20Add more encodings for Thumb instructions.Bill Wendling
2010-11-20Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the sameBill Wendling
2010-11-19Fix ARM LDR* post-indexed operand encoding.Jim Grosbach
2010-11-19Encodings for the compare instructions.Bill Wendling
2010-11-19The Vm and Vn register fields must be the same for a register-register vmov.Owen Anderson
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