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AgeCommit message (Expand)Author
2011-12-05Simple branch relaxation for Thumb2 Bcc instructions.Jim Grosbach
2011-12-05Tweak ADDrr fix. Bad check for explicit .wJim Grosbach
2011-12-05Thumb2 prefer ADD register encoding T2 to T3 when possible.Jim Grosbach
2011-12-05Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.Jim Grosbach
2011-12-05ARM assembly parsing for the rest of the VMUL data type aliases.Jim Grosbach
2011-12-05Fix previous commit. Oops.Jim Grosbach
2011-12-05Tidy up. No functional change.Jim Grosbach
2011-12-05ARM assmebler parsing for two-operand VMUL instructions.Jim Grosbach
2011-12-04Fix 80-column issues.Bob Wilson
2011-12-03Emit the ctors in the proper order on ARM/EABI.Anton Korobeynikov
2011-12-03[arm-fast-isel] Unaligned stores of floats require special care.Chad Rosier
2011-12-02ARM NEON VEXT aliases for data type suffices.Jim Grosbach
2011-12-02ARM VEXT tighten up operand classes a bit.Jim Grosbach
2011-12-02ARM VST1 single lane assembly parsing.Jim Grosbach
2011-12-02Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky
2011-12-02ARM VLD1 single lane assembly parsing.Jim Grosbach
2011-12-02ARM encoder method needs the physical register number, not the enum.Jim Grosbach
2011-12-02[arm-fast-isel] After promoting a function parameter be sure to update theChad Rosier
2011-12-02Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.Jim Grosbach
2011-12-02ARM start parsing VLD1 single lane instructions.Jim Grosbach
2011-11-30Remove unused variableMatt Beaumont-Gay
2011-11-30ARM parsing for VLD1 all lanes, with writeback.Jim Grosbach
2011-11-30ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach
2011-11-30ARM parsing aliases for VLD1 single register all lanes.Jim Grosbach
2011-11-29Tidy up a bit.Jim Grosbach
2011-11-29Add comment.Jim Grosbach
2011-11-29ARM parsing aliases for data-size suffices on VST1.Jim Grosbach
2011-11-29ARM assembly parsing and encoding for four-register VST1.Jim Grosbach
2011-11-29ARM assembly parsing and encoding for three-register VST1.Jim Grosbach
2011-11-29comment.Andrew Trick
2011-11-29build/CMake: Finish removal of add_llvm_library_dependencies.Daniel Dunbar
2011-11-29Better fix for ARM MOVT relocation encoding of thumb bit.Jim Grosbach
2011-11-28Silence wrong warnings from GCC about variables possibly being usedDuncan Sands
2011-11-26Move code into anonymous namespaces.Benjamin Kramer
2011-11-25ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build.NAKAMURA Takumi
2011-11-18Guard call to getRegForValue with isTypeLegal check to avoid unnecessary work...Chad Rosier
2011-11-17Add TODO comment.Chad Rosier
2011-11-17Dead code.Chad Rosier
2011-11-17Don't unconditionally set the kill flag.Chad Rosier
2011-11-16Generalize the fixup info for ARM mode.Jim Grosbach
2011-11-16Fix encoding of NOP used for padding in ARM mode .align.Jim Grosbach
2011-11-16ARM assembly parsing for shifted register operands for MOV instruction.Jim Grosbach
2011-11-16Clean up debug printing of ARM shifted operands.Jim Grosbach
2011-11-16ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.Jim Grosbach
2011-11-16ARM assembly parsing for RRX mnemonic.Jim Grosbach
2011-11-16Check to make sure we can select the instruction before trying to put theChad Rosier
2011-11-16ARM mode aliases for bitwise instructions w/ register operands.Jim Grosbach
2011-11-16Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.Bob Wilson
2011-11-16lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp al...NAKAMURA Takumi
2011-11-16Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng
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