| Age | Commit message (Expand) | Author |
|---|
| 2013-03-22 | Allow the register scavenger to spill multiple registers | Hal Finkel |
| 2013-02-21 | Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo | Eli Bendersky |
| 2013-01-31 | [PEI] Pass the frame index operand number to the eliminateFrameIndex function. | Chad Rosier |
| 2013-01-02 | Move all of the header files which are involved in modelling the LLVM IR | Chandler Carruth |
| 2012-12-19 | Remove the explicit MachineInstrBuilder(MI) constructor. | Jakob Stoklund Olesen |
| 2012-12-03 | Use the new script to sort the includes of every file under lib. | Chandler Carruth |
| 2012-05-07 | Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). | Jakob Stoklund Olesen |
| 2012-04-20 | Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change s... | Craig Topper |
| 2012-03-17 | Reorder includes to match coding standards. Fix an issue or two exposed by that. | Craig Topper |
| 2012-03-01 | Handle regmasks in Thumb1RegisterInfo::saveScavengerRegister(). | Jakob Stoklund Olesen |
| 2012-02-28 | Enable ARM base pointer when calling functions with large arguments. | Jakob Stoklund Olesen |
| 2012-02-18 | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu |
| 2012-02-07 | Convert assert(0) to llvm_unreachable | Craig Topper |
| 2011-12-07 | Add bundle aware API for querying instruction properties and switch the code | Evan Cheng |
| 2011-10-10 | Fix a regression from r138445. If we're loading from the frame/base pointer | Chad Rosier |
| 2011-08-24 | Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. | Jim Grosbach |
| 2011-08-17 | 80 columns. | Jim Grosbach |
| 2011-08-17 | Tidy up. | Jim Grosbach |
| 2011-08-12 | Silence a bunch (but not all) "variable written but not read" warnings | Duncan Sands |
| 2011-07-20 | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng |
| 2011-07-18 | Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for | Evan Cheng |
| 2011-06-30 | Refact ARM Thumb1 tMOVr instruction family. | Jim Grosbach |
| 2011-06-30 | Thumb1 register to register MOV instruction is predicable. | Jim Grosbach |
| 2011-06-29 | Refactor away tSpill and tRestore pseudos in ARM backend. | Jim Grosbach |
| 2011-06-28 | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng |
| 2011-06-02 | Use TRI::has{Sub,Super}ClassEq() where possible. | Jakob Stoklund Olesen |
| 2011-04-26 | Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on regist... | Jakob Stoklund Olesen |
| 2011-04-18 | Trim a few unneeded includes. | Jim Grosbach |
| 2011-03-31 | Provide a legal pointer register class when targeting thumb1. | Jakob Stoklund Olesen |
| 2011-03-05 | In Thumb1 mode the constant might be materialized via the load from constpool... | Anton Korobeynikov |
| 2011-03-05 | Implement frame unwinding information emission for Thumb1. Not finished yet b... | Anton Korobeynikov |
| 2011-03-05 | Preliminary support for ARM frame save directives emission via MI flags. | Anton Korobeynikov |
| 2011-01-13 | When updating a tSpill/tRestore instruction to be a tSTRr/tLDRr, correctly | Jim Grosbach |
| 2011-01-10 | Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs a... | Anton Korobeynikov |
| 2010-12-21 | If we're not using reg+reg offset we're using reg+imm, set the opcode | Eric Christopher |
| 2010-12-16 | Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi | Bill Wendling |
| 2010-12-15 | Thumb1 had two patterns for the same load-from-constant-pool instruction. | Jim Grosbach |
| 2010-12-15 | If we're changing the frame register to a physical register other than SP, we | Bill Wendling |
| 2010-12-14 | The tLDR et al instructions were emitting either a reg/reg or reg/imm | Bill Wendling |
| 2010-11-19 | Avoid release build warnings. | Benjamin Kramer |
| 2010-11-18 | Move hasFP() and few related hooks to TargetFrameInfo. | Anton Korobeynikov |
| 2010-11-15 | First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ou... | Anton Korobeynikov |
| 2010-11-02 | Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke | Jim Grosbach |
| 2010-10-19 | Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any | Jim Grosbach |
| 2010-09-20 | Simplify ARM callee-saved register handling by removing the distinction | Jim Grosbach |
| 2010-09-03 | Re-apply r112883: | Jim Grosbach |
| 2010-09-03 | Revert "For ARM stack frames that utilize variable sized objects and have eit... | Daniel Dunbar |
| 2010-09-02 | For ARM stack frames that utilize variable sized objects and have either | Jim Grosbach |
| 2010-08-26 | Simplify eliminateFrameIndex() interface back down now that PEI doesn't need | Jim Grosbach |
| 2010-08-19 | Add Thumb1 support for virtual frame indices. | Jim Grosbach |
