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path: root/lib/Target/ARM/ARMInstrThumb.td
AgeCommit message (Expand)Author
2011-08-19Thumb assembly parsing and encoding for LSL(immediate).Jim Grosbach
2011-08-19Thumb assembly parsing and encoding for LDRSB and LDRSH.Jim Grosbach
2011-08-19Thumb assembly parsing and encoding for LDRH.Jim Grosbach
2011-08-19Thumb assembly parsing and encoding for LDRB.Jim Grosbach
2011-08-19Thumb assembly parsing and encoding for LDR(immediate) form T2.Jim Grosbach
2011-08-19Thumb assembly parsing and encoding for LDR(immediate) form T1.Jim Grosbach
2011-08-19Add explanatory comment.Jim Grosbach
2011-08-18Thumb assembly parsing and encoding for LDM instruction.Jim Grosbach
2011-08-18Thumb assembly parsing and encoding for CMP.Jim Grosbach
2011-08-18Thumb instructions CBZ and CBNZ are Thumb2, not THumb1.Jim Grosbach
2011-08-1880 columns.Jim Grosbach
2011-08-17Clean up patterns for Thumb1 system instructions.Jim Grosbach
2011-08-17ARM clean up the imm_sr operand class representation.Jim Grosbach
2011-08-17Thumb assembly parsing and encoding for ADR.Jim Grosbach
2011-08-16Thumb ADD(immediate) parsing support.Jim Grosbach
2011-08-15Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.Owen Anderson
2011-08-09Replace the existing ARM disassembler with a new one based on the FixedLenDec...Owen Anderson
2011-08-08Thumb1 BL instructions encoding 22 bits of displacement, not 21.Owen Anderson
2011-08-08Fix encodings for Thumb ASR and LSR immediate operands. They encode the rang...Owen Anderson
2011-08-03ARM refactoring assembly parsing of memory address operands.Jim Grosbach
2011-08-03Fix broken encoding of tCBNZ.Owen Anderson
2011-08-01Move imm0_255 to ARMInstrInfo.td with the other immediate predicates.Jim Grosbach
2011-07-26ARM parsing and encoding for SVC instruction.Jim Grosbach
2011-07-22Thumb assembly support for SETEND instruction.Jim Grosbach
2011-07-18Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple...Owen Anderson
2011-07-18Mark the Darwin assembler workout as isCodeGenOnly, so that it doesn't cause ...Owen Anderson
2011-07-18Re-apply r135319 with a fix for the constant island pass.Owen Anderson
2011-07-16Revert r135319 in an attempt to get to unbreak testers.Owen Anderson
2011-07-15Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tB...Owen Anderson
2011-07-14Add OperandTypes for Thumb branch targets.Benjamin Kramer
2011-07-13Add a target-indepedent entry to MCInstrDesc to describe the encoded size of ...Owen Anderson
2011-07-13Range checking for CDP[2] immediates.Jim Grosbach
2011-07-13Fix predicates for Thumb co-processor instructions.Jim Grosbach
2011-07-08Mark tBRIND as predicable.Jim Grosbach
2011-07-08Pseudo-ize tBRIND.Jim Grosbach
2011-07-08Make tBX_RET and tBX_RET_vararg predicable.Jim Grosbach
2011-07-08Pseudo-ize tBX_RET and tBX_RET_vararg.Jim Grosbach
2011-07-08Shuffle productions around a bit.Jim Grosbach
2011-07-08Use tPseudoExpand for tTAILJMPrND and tTAILJMPr.Jim Grosbach
2011-07-08Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.Jim Grosbach
2011-07-08Move Thumb tail call pseudos to Thumb.td file.Jim Grosbach
2011-07-08Use TableGen'erated pseudo lowering for ARM.Jim Grosbach
2011-07-01Pseudo-ize t2MOVCC[ri].Jim Grosbach
2011-06-30Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach
2011-06-30Thumb1 register to register MOV instruction is predicable.Jim Grosbach
2011-06-30Pseudo-ize the Thumb tTPsoft instruction.Jim Grosbach
2011-06-30Pseudo-ize the Thumb tPOP_RET instruction.Jim Grosbach
2011-06-29Refactor away tSpill and tRestore pseudos in ARM backend.Jim Grosbach
2011-06-27ARM Assembly support for Thumb mov-immediate.Jim Grosbach
2011-06-21Teach dag combine to match halfword byteswap patterns.Evan Cheng
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