| Age | Commit message (Expand) | Author |
|---|
| 2013-04-01 | ARM Scheduler Model: Add resources instructions, map resources in subtargets | Arnold Schwaighofer |
| 2013-03-26 | Revert ARM Scheduler Model: Add resources instructions, map resources | Arnold Schwaighofer |
| 2013-03-26 | ARM Scheduler Model: Add resources instructions, map resources in subtargets | Arnold Schwaighofer |
| 2013-02-23 | ARM: Convenience aliases for 'srs*' instructions. | Jim Grosbach |
| 2013-02-05 | Move MRI liveouts to ARM return instructions. | Jakob Stoklund Olesen |
| 2013-01-30 | Add a special ARM trap encoding for NaCl. | Eli Bendersky |
| 2012-11-29 | Added atomic 64 min/max/umin/umax instrinsics support in the ARM backend. | Silviu Baranga |
| 2012-11-16 | Remove hard coded registers in ARM ldrexd and strexd instructions | Weiming Zhao |
| 2012-11-06 | Mark the Int_eh_sjlj_dispatchsetup pseudo instruction as clobbering all | Chad Rosier |
| 2012-10-24 | Fix a miscompilation caused by a typo. When turning a adde with negative value | Evan Cheng |
| 2012-09-29 | Add LLVM support for Swift. | Bob Wilson |
| 2012-09-18 | MOVi16 (movw) is only legal on cpus with V6T2 support. rdar://12300648 | Evan Cheng |
| 2012-09-05 | Remove predicated pseudo-instructions. | Jakob Stoklund Olesen |
| 2012-09-04 | Patch to implement UMLAL/SMLAL instructions for the ARM architecture | Arnold Schwaighofer |
| 2012-08-28 | Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ... | Jakob Stoklund Olesen |
| 2012-08-27 | Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM. | Jakob Stoklund Olesen |
| 2012-08-24 | Explicitly mark LEApcrel pseudos with hasSideEffects. | Jakob Stoklund Olesen |
| 2012-08-24 | Add missing SDNPSideEffect flags. | Jakob Stoklund Olesen |
| 2012-08-24 | Fix undefined behavior (negation of INT_MIN) in ARM backend. | Richard Smith |
| 2012-08-16 | Add ADD and SUB to the predicable ARM instructions. | Jakob Stoklund Olesen |
| 2012-08-16 | Handle ARM MOVCC optimization in PeepholeOptimizer. | Jakob Stoklund Olesen |
| 2012-08-15 | Fold predicable instructions into MOVCC / t2MOVCC. | Jakob Stoklund Olesen |
| 2012-08-15 | Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows una... | Evan Cheng |
| 2012-08-15 | Add missing Rfalse operand to the predicated pseudo-instructions. | Jakob Stoklund Olesen |
| 2012-08-12 | Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARM | Arnold Schwaighofer |
| 2012-08-09 | Patch to implement UMLAL/SMLAL instructions for the ARM architecture | Arnold Schwaighofer |
| 2012-08-02 | ARM: Tidy up. Remove unused template parameters. | Jim Grosbach |
| 2012-08-02 | Fix #13241, a bug around shift immediate operand for ARM instruction ADR. | Jiangning Liu |
| 2012-08-01 | ARM: Remove redundant instalias. | Jim Grosbach |
| 2012-08-01 | Clean up formatting. | Jim Grosbach |
| 2012-07-13 | Remove variable_ops from ARM call instructions. | Jakob Stoklund Olesen |
| 2012-06-23 | (sub X, imm) gets canonicalized to (add X, -imm) | Evan Cheng |
| 2012-06-22 | ARM: Add a better diagnostic for some out of range immediates. | Jim Grosbach |
| 2012-06-22 | Rename -allow-excess-fp-precision flag to -fuse-fp-ops, and switch from a | Lang Hames |
| 2012-06-19 | Add DAG-combines for aggressive FMA formation. | Lang Hames |
| 2012-06-18 | ARM: Define generic HINT instruction. | Jim Grosbach |
| 2012-06-11 | Re-enable the CMN instruction. | Bill Wendling |
| 2012-06-02 | Fix typos found by http://github.com/lyda/misspell-check | Benjamin Kramer |
| 2012-06-01 | ARM: properly handle alignment for struct byval. | Manman Ren |
| 2012-06-01 | ARM: support struct byval in llvm | Manman Ren |
| 2012-05-17 | Remove incorrect pattern for ARM SMML instruction. | Tim Northover |
| 2012-05-11 | Added the missing bit definition for the 4th bit of the STR (post reg) instru... | Silviu Baranga |
| 2012-04-24 | ARM: improved assembler diagnostics for missing CPU features. | Jim Grosbach |
| 2012-04-23 | Tidy up. 80 columns, whitespace, et. al. | Jim Grosbach |
| 2012-04-19 | ARM let TableGen handle a few two-operand aliases. | Jim Grosbach |
| 2012-04-18 | Added support for disassembling unpredictable swp/swpb ARM instructions. | Silviu Baranga |
| 2012-04-18 | Fix the bahavior of the disassembler when decoding unpredictable mrs instruct... | Silviu Baranga |
| 2012-04-18 | Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ... | Silviu Baranga |
| 2012-04-18 | Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocess... | Silviu Baranga |
| 2012-04-18 | Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instruct... | Silviu Baranga |
