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by creating TargetConstants during instruction selection instead of during
legalization.
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multiple instructions, the expansion is done during selection so there is
no need to do anything special during legalization.
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something similar)
and register spills.
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This fixes PR5031. Unfortunately, there is no small testcase :(
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blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.
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sdisel will use to properly complete phi nodes.
Not functionality change yet.
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Radar 7200803. (This should also fix the
SingleSource/UnitTests/Vector/sumarray-dbl test.)
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See the bug report for details.
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non-pic mode. rdar://7187172.
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makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.
Objective C++ code could generate function names that broke the previous
scheme. This fixes that.
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Remove the assertion and generalize the code for ARM NEON stuff.
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bunch of nasty code in ARM asm printer.
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scalar_to_vector is fully legal now
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No idea whether this is profitable or not.
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The instructions can be selected directly from the intrinsics. We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.
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construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
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now using shuffles instead of intrinsics.
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perfectshuffle-generated table.
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masks, so legalizer won't infinite cycle
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This is derived from a patch by Anton Korzh. I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.
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support unaligned mem access only for certain types. (Should it be size
instead?)
ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.
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libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.
Patch by Sandeep!
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implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78995 91177308-0d34-0410-b5e6-96231b3b80d8
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scalar_to_vector. Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.
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target-specific VDUPLANE nodes. This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.
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to fix it tonight.
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