aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/ARM/ARMISelLowering.cpp
AgeCommit message (Collapse)Author
2012-08-13Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ↵Nadav Rotem
ISDNode has more than one user. rdar://11876519 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARMArnold Schwaighofer
architecture It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7 thumb O3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161736 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-12Change addTypeForNeon to use MVT instead of EVT so all the calls to ↵Craig Topper
getSimpleVT can be removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161735 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-09Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer
This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161581 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03Fall back to selection DAG isel for calls to builtin functions.Bob Wilson
Fast isel doesn't currently have support for translating builtin function calls to target instructions. For embedded environments where the library functions are not available, this is a matter of correctness and not just optimization. Most of this patch is just arranging to make the TargetLibraryInfo available in fast isel. <rdar://problem/12008746> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161232 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03Add support for the ARM GHC calling convention, this patch was in 3.0,Eric Christopher
but somehow managed to be dropped later. Patch by Karel Gardas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25ARM: Don't assume an SDNode is a constant.Jim Grosbach
Before accessing a node as a ConstandSDNode, make sure it actually is one. No testcase of non-trivial size. rdar://11948669 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160735 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18Fix ARMTargetLowering::isLegalAddImmediate to consider thumb encodings.Andrew Trick
Based on Evan's suggestion without a commitable test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160441 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18whitespaceAndrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160440 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-18ARM: use NOEN loads and stores if possible when handling struct byval.Manman Ren
This change is to be enabled in clang. rdar://9877866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158684 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-15ARM: optimization for sub+abs.Manman Ren
This patch will optimize abs(x-y) FROM sub, movs, rsbmi TO subs, rsbmi For abs, we will use cmp instead of movs. This is necessary because we already have an existing peephole pass which optimizes away cmp following sub. rdar: 11633193 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158551 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-11Re-enable the CMN instruction.Bill Wendling
We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01ARM: properly handle alignment for struct byval.Manman Ren
Factor out the expansion code into a function. This change is to be enabled in clang. rdar://9877866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157830 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-01ARM: support struct byval in llvmManman Ren
We handle struct byval by inserting a pseudo op, which will be expanded to a loop at ExpandISelPseudos. A separate patch for clang will be submitted to enable struct byval. rdar://9877866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157793 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-25Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski
to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-20Use the right register class for LDRrs.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-05Add a new target hook "predictableSelectIsExpensive".Benjamin Kramer
This will be used to determine whether it's profitable to turn a select into a branch when the branch is likely to be predicted. Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM. I'm not entirely happy with the name of this flag, suggestions welcome ;) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156233 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Pacify GCC's -Wreturn-typeMatt Beaumont-Gay
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156189 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-04Make ARM and Mips use TargetMachine::getTLSModel()Hans Wennborg
This moves the logic for selecting a TLS model to a single place, instead of the previous three (ARM, Mips, and X86 which already uses this function). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156162 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-30Don't introduce illegal types when creating vmull operations. <rdar://11324364>Bob Wilson
ARM BUILD_VECTORs created after type legalization cannot use i8 or i16 operands, since those types are not legal. Instead use i32 operands, which will be implicitly truncated by the BUILD_VECTOR to match the element type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-20Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper
since they are equivalent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Handle llvm.fma.* intrinsics. rdar://10914096Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154439 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-10Fix a long standing tail call optimization bug. When a libcall is emittedEvan Cheng
legalizer always use the DAG entry node. This is wrong when the libcall is emitted as a tail call since it effectively folds the return node. If the return node's input chain is not the entry (i.e. call, load, or store) use that as the tail call input chain. PR12419 rdar://9770785 rdar://11195178 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154370 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-09When performing a truncating store, it's possible to rearrange the data Chad Rosier
in-register, such that we can use a single vector store rather then a series of scalar stores. For func_4_8 the generated code vldr d16, LCPI0_0 vmov d17, r0, r1 vadd.i16 d16, d17, d16 vmov.u16 r0, d16[3] strb r0, [r2, #3] vmov.u16 r0, d16[2] strb r0, [r2, #2] vmov.u16 r0, d16[1] strb r0, [r2, #1] vmov.u16 r0, d16[0] strb r0, [r2] bx lr becomes vldr d16, LCPI0_0 vmov d17, r0, r1 vadd.i16 d16, d17, d16 vuzp.8 d16, d17 vst1.32 {d16[0]}, [r2, :32] bx lr I'm not fond of how this combine pessimizes 2012-03-13-DAGCombineBug.ll, but I couldn't think of a way to judiciously apply this combine. This ldrh r0, [r0, #4] strh r0, [r1] becomes vldr d16, [r0] vmov.u16 r0, d16[2] vmov.32 d16[0], r0 vuzp.16 d16, d17 vst1.32 {d16[0]}, [r1, :32] PR11158 rdar://10703339 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-09Update comments and remove unnecessary isVolatile() check.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154336 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-06Tidy up. 80 columns.Jim Grosbach
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-06There is no portable std::abs overload for int64_t, use the llvm::abs64Chandler Carruth
which exists for this purpose. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154199 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-06Allow negative immediates in ARM and Thumb2 compares.Jakob Stoklund Olesen
ARM and Thumb2 mode can use cmn instructions to compare against negative immediates. Thumb1 mode can't. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154183 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-04Always compute all the bits in ComputeMaskedBits.Rafael Espindola
This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-30ARM target should allow codegenprep to duplicate ret instructions to enable ↵Evan Cheng
tailcall opt. rdar://11140249 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153717 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-29Try using vmov.i32 to materialize FP32 constants that can't be materialized byLang Hames
vmov.f32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153696 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-27Remove unnecessary llvm:: qualificationsCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-26Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.hCraig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153422 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-25Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153421 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-19Perform mul combine when multiplying wiht negative constants.Anton Korobeynikov
Patch by Weiming Zhao! This fixes PR12212 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153049 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-17Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-15Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints onLang Hames
register allocation by allowing all 32 D-registers to be used. Patch by Cameron Zwarich. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-11Convert more static tables of registers used by calling convention to ↵Craig Topper
uint16_t to reduce space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-04Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper
size of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
2012-03-01Neuter the optimization I implemented with r107852 and r108258 which turn someEvan Cheng
floating point equality comparisons into integer ones with -ffast-math. The issue is the optimization causes +0.0 != -0.0. Now the optimization is only done when one side is known to be 0.0. The other side's sign bit is masked off for the comparison. rdar://10964603 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151861 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng
direct call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar
prediction. ...", it is breaking the Clang build during the Compiler-RT part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-28Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng
the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24Switch ARM target to register masks.Jakob Stoklund Olesen
I'll let the buildbots determine the compile time improvements from this change, but 464.h264ref has 5% faster codegen at -O2. This patch does cause some assembly changes. Branch folding can make different decisions about calls with dead return values. CriticalAntiDepBreaker may choose different registers because its liveness tracking is affected. MachineCopyPropagation may sometimes leave a dead copy behind. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151331 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-24When emitting a cmp with 0 for a lowered select, mask out the highDan Gohman
bits of the value carying the boolean condition, as their contents are undefined. This fixes rdar://10887484. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151310 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16 bitsEvan Cheng
of x are zero. This optimizes rev + lsr 16 to rev16. rdar://10750814 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151230 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23Optimize a couple of common patterns involving conditional moves where the falseEvan Cheng
value is zero. Instead of a cmov + op, issue an conditional op instead. e.g. cmp r9, r4 mov r4, #0 moveq r4, #1 orr lr, lr, r4 should be: cmp r9, r4 orreq lr, lr, #1 That is, optimize (or x, (cmov 0, y, cond)) to (or.cond x, y). Similarly extend this to xor as well as (and x, (cmov -1, y, cond)) => (and.cond x, y). It's possible to extend this to ADD and SUB but I don't think they are common. rdar://8659097 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151224 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-22Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper
to static data that should not be modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-21Proper support for a bastardized darwin-eabi hybird ABI.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151083 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-20Improve generated code for extending loads and some trunc stores on ARM.James Molloy
Teach TargetSelectionDAG about lengthening loads for vector types and set v4i8 as legal. Allow FP_TO_UINT for v4i16 from v4i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150956 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3-70-g09d2 (git 2.46.0) at 2026-02-10 19:51:00 +0000