| Age | Commit message (Expand) | Author |
|---|
| 2011-12-09 | ARM assembly parsing and encoding for VLD2 with writeback. | Jim Grosbach |
| 2011-11-29 | ARM assembly parsing and encoding for four-register VST1. | Jim Grosbach |
| 2011-11-29 | ARM assembly parsing and encoding for three-register VST1. | Jim Grosbach |
| 2011-10-31 | ARM VST1 w/ writeback assembly parsing and encoding. | Jim Grosbach |
| 2011-10-27 | Also set addrmode6 alignment when align==size. | Jakob Stoklund Olesen |
| 2011-10-27 | ARM isel for vld1, opcode selection for register stride post-index pseudos. | Jim Grosbach |
| 2011-10-24 | ARM refactor am6offset usage for VLD1. | Jim Grosbach |
| 2011-10-18 | Fix misc warnings. Patch by Joe Abbey. | Eli Friedman |
| 2011-10-10 | Reapply r141365 now that PR11107 is fixed. | Bill Wendling |
| 2011-10-10 | Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to | Bill Wendling |
| 2011-10-08 | Disable ABS optimization for Thumb1 target, we don't have necessary instructi... | Anton Korobeynikov |
| 2011-10-07 | Peephole optimization for ABS on ARM. | Anton Korobeynikov |
| 2011-10-05 | Always merge profitable shifts on A9, not just when they have a single use. | Cameron Zwarich |
| 2011-10-05 | Remove a check from ARM shifted operand isel helper methods, which were blocking | Cameron Zwarich |
| 2011-10-05 | Add braces around something that throws me for a loop. | Cameron Zwarich |
| 2011-10-05 | There is no point in setting out-parameters for a ComplexPattern function when | Cameron Zwarich |
| 2011-09-23 | Also match negative offsets for addrmode3 and addrmode5. | Jakob Stoklund Olesen |
| 2011-09-13 | Tidy up a few 80 column violations. | Jim Grosbach |
| 2011-08-31 | When performing instruction selection for LDR_PRE_IMM/LDRB_PRE_IMM, we still ... | Owen Anderson |
| 2011-08-31 | 64-bit atomic cmpxchg for ARM. | Eli Friedman |
| 2011-08-31 | Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next. | Eli Friedman |
| 2011-08-29 | addrmode_imm12 and addrmode2_offset encode their immediate values differently... | Owen Anderson |
| 2011-08-26 | Fix ARM codegen breakage caused by r138653. | Owen Anderson |
| 2011-08-26 | invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We w... | Owen Anderson |
| 2011-08-24 | Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. | Jim Grosbach |
| 2011-08-05 | ARM refactor indexed store instructions. | Jim Grosbach |
| 2011-07-27 | ARM parsing and encoding of SBFX and UBFX. | Jim Grosbach |
| 2011-07-26 | Split am2offset into register addend and immediate addend forms, necessary fo... | Owen Anderson |
| 2011-07-22 | Fix test failures caused by my so_reg refactoring. | Owen Anderson |
| 2011-07-21 | Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn n... | Owen Anderson |
| 2011-07-21 | Split up the ARM so_reg ComplexPattern into so_reg_reg and so_reg_imm, allowi... | Owen Anderson |
| 2011-07-20 | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng |
| 2011-06-28 | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng |
| 2011-06-16 | Change the REG_SEQUENCE SDNode to take an explict register class ID as its fi... | Owen Anderson |
| 2011-05-28 | Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs | Bruno Cardoso Lopes |
| 2011-04-29 | Zap a couple now-unused functions. | Eli Friedman |
| 2011-04-19 | This patch combines several changes from Evan Cheng for rdar://8659675. | Bob Wilson |
| 2011-04-19 | Do not lose mem_operands while lowering VLD / VST intrinsics. | Evan Cheng |
| 2011-03-18 | Reduce code duplication. | Owen Anderson |
| 2011-03-14 | Generate a VTBL instruction instead of a series of loads and stores when we | Bill Wendling |
| 2011-03-11 | Remove dead code. These ARM instruction definitions no longer exist. | Jim Grosbach |
| 2011-03-05 | Remove unused conditional negate operations. | Bob Wilson |
| 2011-02-25 | Add patterns to use post-increment addressing for Neon VST1-lane instructions. | Bob Wilson |
| 2011-02-13 | Enhance ComputeMaskedBits to know that aligned frameindexes | Chris Lattner |
| 2011-02-07 | Add codegen support for using post-increment NEON load/store instructions. | Bob Wilson |
| 2011-02-07 | Change VLD3/4 and VST3/4 for quad registers to not update the address register. | Bob Wilson |
| 2011-01-20 | Sorry, several patches in one. | Evan Cheng |
| 2011-01-19 | ARM/ISel: Factor out isScaledConstantInRange() helper. | Daniel Dunbar |
| 2011-01-17 | Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. | Evan Cheng |
| 2011-01-01 | Model operand restrictions of mul-like instructions on ARMv5 via | Anton Korobeynikov |
