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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152260 91177308-0d34-0410-b5e6-96231b3b80d8
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ScheduleDAGInstrs will be the main interface for MI-level
schedulers. Make sure it's readable: one page of protected fields, one
page of public methids.
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ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted.
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We had half the API with one convention, half with another. Now was a
good time to clean it up.
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This one is particularly annoying because the hashing algorithm is
highly specialized, with a strange "equivalence" definition that subsets
the fields involved.
Still, this looks at the exact same set of data as the old code, but
without bitwise or-ing over parts of it and other mixing badness. No
functionality changed here. I've left a substantial fixme about the fact
that there is a cleaner and more principled way to do this, but it
requires making the equality definition actual stable for particular
types...
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the DebugLoc information can be maintained throughout by grabbing the DebugLoc
before the RemoveBranch and then passing the result to the InsertBranch.
Patch by Andrew Stanford-Jason!
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ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation.
ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class.
ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target.
Specific changes:
- Removed driver code from ScheduleDAG. clearDAG is the only interface needed.
- Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls.
- Added ScheduleDAGInstrs::begin()/end() public API.
- Moved Sequence into the driver layer, which is specific to the scheduling algorithm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152208 91177308-0d34-0410-b5e6-96231b3b80d8
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ScheduleDAG has nothing to do with how the instructions are scheduled.
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ScheduleDAG will not refer to the scheduled instruction sequence.
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ScheduleDAG will not refer to the scheduled instruction sequence.
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Soon, ScheduleDAG will not refer to the BB.
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diagnostics.
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the target interface.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152173 91177308-0d34-0410-b5e6-96231b3b80d8
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as well as completely defined classes.
This fixes rdar://10956070
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performance regression (due to increased register pressure from overly aggressive pre-inc formation).
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providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152079 91177308-0d34-0410-b5e6-96231b3b80d8
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Used to allow context sensitive printing of super-register or sub-register
references.
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Patch by Sean Silva!
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static data size.
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The first def of a virtual register cannot also read the register.
Assert on such bad machine code instead of trying to fix it.
TwoAddressInstructionPass should never create code like that.
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We are already setting <undef> flags, and that is good enough. The
<imp-def> operands don't mean anything any more.
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static data size.
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size of static data.
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to the string table for the function name, not the function name.
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The inline table needs to be constructed ahead of time so that it doesn't try to
create new strings while we're emitting everything.
This reverts commit a8ff9bccb399183cdd5f1c3cec2bda763664b4b0.
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fixups that are being used to determine section offsets. Reduces
the total number of fixups by 50% for a non-trivial testcase.
Part of rdar://10413936
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though they could have sideeffects.
Only allow log2/exp2 to be converted to an intrinsic if they are declared "readnone".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151807 91177308-0d34-0410-b5e6-96231b3b80d8
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Simply treat bundles as instructions. Spill code is inserted between
bundles, never inside a bundle. Rewrite all operands in a bundle at
once.
Don't attempt and memory operand folding inside bundles.
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This allows the function to be inlined, and makes it suitable for use in
getInstructionIndex().
Also provide a const version. C++ is great for touch typing practice.
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While we're at it - don't copy vreg implicit operands while rematerializing.
This fixes PR12138.
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optimization, making the lives of later passes easier.
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This function does more or less the same as
MI::readsWritesVirtualRegister(), but it supports bundles as well.
It also determines if any constraint requires reading and writing
operands to use the same register. Most clients want to know.
Use the more modern MO.readsReg() instead of trying to sort out undefs
and partial redefines. Stop supporting the extra full <imp-def> operand
as an alternative to <def,undef> sub-register defines.
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Extract a base class and provide four specific sub-classes for iterating
over const/non-const bundles/instructions.
This eliminates the mystery bool constructor argument.
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