diff options
| author | Craig Topper <craig.topper@gmail.com> | 2012-03-04 10:16:38 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-03-04 10:16:38 +0000 |
| commit | b6632ba380cf624e60fe16b03d6e21b05dd07724 (patch) | |
| tree | 5b3ca53e138cd22a7b04e0e034b0a952d0972de7 /lib/CodeGen | |
| parent | 015f228861ef9b337366f92f637d4e8d624bb006 (diff) | |
Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/AllocationOrder.cpp | 2 | ||||
| -rw-r--r-- | lib/CodeGen/RegAllocPBQP.cpp | 2 | ||||
| -rw-r--r-- | lib/CodeGen/RegisterClassInfo.cpp | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/lib/CodeGen/AllocationOrder.cpp b/lib/CodeGen/AllocationOrder.cpp index 1005f102be..87f64311a6 100644 --- a/lib/CodeGen/AllocationOrder.cpp +++ b/lib/CodeGen/AllocationOrder.cpp @@ -41,7 +41,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg, if (HintPair.first) { const TargetRegisterInfo &TRI = VRM.getTargetRegInfo(); // The remaining allocation order may depend on the hint. - ArrayRef<unsigned> Order = + ArrayRef<uint16_t> Order = TRI.getRawAllocationOrder(RC, HintPair.first, Hint, VRM.getMachineFunction()); if (Order.empty()) diff --git a/lib/CodeGen/RegAllocPBQP.cpp b/lib/CodeGen/RegAllocPBQP.cpp index a36eeff6ea..f15574c8cb 100644 --- a/lib/CodeGen/RegAllocPBQP.cpp +++ b/lib/CodeGen/RegAllocPBQP.cpp @@ -216,7 +216,7 @@ std::auto_ptr<PBQPRAProblem> PBQPBuilder::build(MachineFunction *mf, // Compute an initial allowed set for the current vreg. typedef std::vector<unsigned> VRAllowed; VRAllowed vrAllowed; - ArrayRef<unsigned> rawOrder = trc->getRawAllocationOrder(*mf); + ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(*mf); for (unsigned i = 0; i != rawOrder.size(); ++i) { unsigned preg = rawOrder[i]; if (!reservedRegs.test(preg)) { diff --git a/lib/CodeGen/RegisterClassInfo.cpp b/lib/CodeGen/RegisterClassInfo.cpp index 474b011603..58b1681b0b 100644 --- a/lib/CodeGen/RegisterClassInfo.cpp +++ b/lib/CodeGen/RegisterClassInfo.cpp @@ -85,7 +85,7 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { // FIXME: Once targets reserve registers instead of removing them from the // allocation order, we can simply use begin/end here. - ArrayRef<unsigned> RawOrder = RC->getRawAllocationOrder(*MF); + ArrayRef<uint16_t> RawOrder = RC->getRawAllocationOrder(*MF); for (unsigned i = 0; i != RawOrder.size(); ++i) { unsigned PhysReg = RawOrder[i]; // Remove reserved registers from the allocation order. |