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AgeCommit message (Expand)Author
2012-03-16ScheduleDAGInstrs: When adding uses we add them into a set that's empty at th...Benjamin Kramer
2012-03-16Limit the number of memory operands in MachineInstr to 2^16 and store the num...Benjamin Kramer
2012-03-16CriticalAntiDepBreaker: BasicBlock::size is an expensive operation, reuse the...Benjamin Kramer
2012-03-16misched: add DAG edges from vreg defs to ExitSU.Andrew Trick
2012-03-16Revert r152705, which reapplied r152486 as this appears to be causing failuresChad Rosier
2012-03-16Revert r152613 (and r152614), "Inline the d'tor and add an anchor instead." f...NAKAMURA Takumi
2012-03-15For types with a parent of the compile unit make sure and emitEric Christopher
2012-03-15We actually handle AllocaInst via getRegForValue below just fine.Eric Christopher
2012-03-15Add some debugging output into fast isel as well.Eric Christopher
2012-03-15Add another debug statement.Eric Christopher
2012-03-15Tabs.Eric Christopher
2012-03-15Typo.Eric Christopher
2012-03-15When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, add...Nadav Rotem
2012-03-15Revert the removal of DW_AT_MIPS_linkage_name when we aren't puttingEric Christopher
2012-03-15Add a xform to the DAG combiner.Bill Wendling
2012-03-14Silence operator precedence warnings.Benjamin Kramer
2012-03-14Reapply r152486 with a fix for the nightly testers.Bill Wendling
2012-03-14Insert the debugging instructions in one fell-swoop so that it doesn't call theBill Wendling
2012-03-14misched: implemented a framework for top-down or bottom-up scheduling.Andrew Trick
2012-03-14misched commentsAndrew Trick
2012-03-14Remove the DW_AT_MIPS_linkage name attribute when we don't need itEric Christopher
2012-03-13Fortify r152675 a bit. Although I'm not able to come up with a test case that...Evan Cheng
2012-03-13DAG combine incorrectly optimize (i32 vextract (v4i16 load $addr), c) toEvan Cheng
2012-03-13s/SjLjEHPass/SjLjEHPrepare/Bill Wendling
2012-03-13Add a return type.Bill Wendling
2012-03-13Inline the d'tor and add an anchor instead.Bill Wendling
2012-03-13Refactor the SelectionDAG's 'dump' methods into their own .cpp file.Bill Wendling
2012-03-13Fixed typo in comment.Lang Hames
2012-03-12Revert due to nightly test failures.Bill Wendling
2012-03-11DwarfDebug: Store the filename/dirname pair as a zero-separated string in a s...Benjamin Kramer
2012-03-11llvm::SwitchInstStepan Dyatkovskiy
2012-03-10Microoptimize getVRegDef. def_begin isn't free, don't compute it twice.Benjamin Kramer
2012-03-10Implement a more intelligent way of spilling uses across an invoke boundary.Bill Wendling
2012-03-10Report the defining instruction.Jakob Stoklund Olesen
2012-03-10Add SSA verification to MachineVerifier.Jakob Stoklund Olesen
2012-03-10Use SmallPtrSet instead of DenseSet.Jakob Stoklund Olesen
2012-03-10Give dagcombiner's worklist some inline capacity.Benjamin Kramer
2012-03-09Assert on SSA errors in LiveVariables.Jakob Stoklund Olesen
2012-03-09misched: handle scheduler that insert instructions at empty region boundaries.Andrew Trick
2012-03-09misched: handle scheduling region boundaries nicely.Andrew Trick
2012-03-09misched interface: rename Begin/End to RegionBegin/RegionEnd since they are n...Andrew Trick
2012-03-09misched commentsAndrew Trick
2012-03-09revert 152356: verify misched changes using -misched=shuffle.Andrew Trick
2012-03-09misched: allow the default scheduler to be one chosen by the target.Andrew Trick
2012-03-09Cache MBB->begin. It's possible the scheduler / bundler may change MBB->begin().Evan Cheng
2012-03-08Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper
2012-03-08Taken into account Duncan's comments for r149481 dated by 2nd Feb 2012:Stepan Dyatkovskiy
2012-03-08misched interface: Expose the MachineScheduler pass.Andrew Trick
2012-03-07Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface.Andrew Trick
2012-03-07misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick