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Patch graciously contributed by Reid Spencer!
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ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.
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instead of randomly groping about inside its outEdges array.
Make SchedGraph::addDummyEdges() use getNumOutEdges() instead of
outEdges.size().
Get rid of ifdefed-out code in SchedGraph::buildGraph().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11238 91177308-0d34-0410-b5e6-96231b3b80d8
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the Virt2PhysRegMap std::map with an std::vector. This speeds up the
register allocator another (almost) 40%, from .72->.45s in a release build
of LLC on 253.perlbmk.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11219 91177308-0d34-0410-b5e6-96231b3b80d8
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speeds up livevar from .48/.32s -> .45/.31s in LLC on perlbmk
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11217 91177308-0d34-0410-b5e6-96231b3b80d8
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This speeds up live variables a lot, from .60/.39s -> .47/.26s in LLC, for
the first/second pass respectively.
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from physical registers, and they are always dense, it makes sense to not have
a ton of RBtree overhead. This change speeds up regalloclocal about ~30% on
253.perlbmk, from .35s -> .27s in the JIT (in LLC, it goes from .74 -> .55).
Now live variable analysis is the slowest codegen pass. Of course it doesn't
help that we have to run it twice, because regalloclocal doesn't update it,
but even if it did it would be the slowest pass (now it's just the 2x slowest
pass :(
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of the virtual register to certain functions.
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slots each. As a concequence they get numbered as 0, 2, 4 and so
on. The first slot is used for operand uses and the second for
defs. Here's an example:
0: A = ...
2: B = ...
4: C = A + B ;; last use of A
The live intervals should look like:
A = [1, 5)
B = [3, x)
C = [5, y)
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access. Rather we only have to do it on the creation of the interval.
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operand of the instruction and thus simplify the register allocation.
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spilled, A was loaded from its stack location twice. This fixes the bug.
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outside of loops = 0.
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much better when I get rid of the reserved registers.
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registers (not as the max number of registers).
Change toSpill from a std::set into a std::vector<bool>.
Use the reverse iterator adapter to do a reverse scan of allocatable
registers.
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where appropriate.
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MRegisterInfo::isVirtualRegister.
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method
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Fix a spello
Tighten up the assertion checking
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11036 91177308-0d34-0410-b5e6-96231b3b80d8
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* Turn a bunch of instance variables into automatic variables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11035 91177308-0d34-0410-b5e6-96231b3b80d8
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Move Passes.h (which defines the interface to this file) to the top.
Move statistics to the top of the file.
Add a comment
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any test cases :-)
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of a linear search to find the first range for comparisons. This cuts
down the linear scan register allocator running time by a factor of 3
in 254.perlbmk and by a factor of 2.2 in 176.gcc.
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the patch.
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Simplification of LiveIntervals::Interval::overlaps() and addition of
examples to overlaps() and liveAt() to make them clearer.
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Implement LiveVariables::getIndexMachineBasicBlock
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choose an ostream.
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when joining we need to check if we overlap with the second interval
or any of its aliases.
Also make joining intervals the default.
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is a move between two registers, at least one of the registers is
virtual and the two live intervals do not overlap.
This results in about 40% reduction in intervals, 30% decrease in the
register allocators running time and a 20% increase in peephole
optimizations (mainly move eliminations).
The option can be enabled by passing -join-liveintervals where
appropriate.
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with the current one.
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