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Age	Commit message (Expand)	Author
2011-02-04	Introducing a new method of tracking register pressure. We can't	Andrew Trick
2011-01-27	Remove a temporary workaround for a lencod miscompile. Depends on the fix in ...	Andrew Trick
2011-01-24	Temporarily workaround JM/lencod miscompile (SIGSEGV).	Andrew Trick
2011-01-21	Enable support for precise scheduling of the instruction selection	Andrew Trick
2011-01-21	Convert -enable-sched-cycles and -enable-sched-hazard to -disable	Andrew Trick
2011-01-20	Selection DAG scheduler register pressure heuristic fixes.	Andrew Trick
2011-01-14	Support for precise scheduling of the instruction selection DAG,	Andrew Trick
2010-12-24	Minor cleanup related to my latest scheduler changes.	Andrew Trick
2010-12-24	Fix a few cases where the scheduler is not checking for phys reg copies. The ...	Andrew Trick
2010-12-24	Various bits of framework needed for precise machine-level selection	Andrew Trick
2010-12-23	flags -> glue for selectiondag	Chris Lattner
2010-12-23	Reorganize ListScheduleBottomUp in preparation for modeling machine cycles an...	Andrew Trick
2010-12-23	Converted LiveRegCycles to LiveRegGens. It's easier to work with and allows m...	Andrew Trick
2010-12-23	In CheckForLiveRegDef use TRI->getOverlaps.	Andrew Trick
2010-12-23	Fixes PR8823: add-with-overflow-128.ll	Andrew Trick
2010-12-21	In DelayForLiveRegsBottomUp, handle instructions that read and write	Andrew Trick
2010-12-21	whitespace	Andrew Trick
2010-12-21	rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for	Chris Lattner
2010-12-20	Fix a bug in the scheduler's handling of "unspillable" vregs.	Chris Lattner
2010-12-20	the result of CheckForLiveRegDef is dead, remove it.	Chris Lattner
2010-11-03	Two sets of changes. Sorry they are intermingled.	Evan Cheng
2010-10-29	Avoiding overly aggressive latency scheduling. If the two nodes share an	Evan Cheng
2010-07-26	The "excess register pressure" returned by HighRegPressure() is not accurate ...	Evan Cheng
2010-07-26	Pacify gcc-4.5 which wrongly thinks that RExcess (passed as the Excess parame...	Duncan Sands
2010-07-25	Add comments.	Evan Cheng
2010-07-25	Fix crashes when scheduling a CopyToReg node -- getMachineOpcode asserts on	Bob Wilson
2010-07-24	Add an ILP scheduler. This is a register pressure aware scheduler that's	Evan Cheng
2010-07-23	- Allow target to specify when is register pressure "too high". In most cases,	Evan Cheng
2010-07-22	Re-apply r109079 with fix.	Evan Cheng
2010-07-22	Revert r109079, which broke a lot of CodeGen tests.	Owen Anderson
2010-07-22	Initialize RegLimit only when register pressure is being tracked.	Evan Cheng
2010-07-21	More register pressure aware scheduling work.	Evan Cheng
2010-07-21	Teach bottom up pre-ra scheduler to track register pressure. Work in progress.	Evan Cheng
2010-06-29	Add a VT argument to getMinimalPhysRegClass and replace the copy related uses	Rafael Espindola
2010-05-30	Use `llvm::next' instead of `next' to make VC++ 2010 happy.	Oscar Fuentes
2010-05-28	Fix some latency computation bugs: if the use is not a machine opcode do not ...	Evan Cheng
2010-05-26	Eliminate the use of PriorityQueue and just use a std::vector,	Dan Gohman
2010-05-26	Delete an unused function.	Dan Gohman
2010-05-26	Change push_all to a non-virtual function and implement it in the	Dan Gohman
2010-05-21	Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.	Evan Cheng
2010-05-20	Allow targets more controls on what nodes are scheduled by reg pressure, what...	Evan Cheng
2010-05-20	Add a hybrid bottom up scheduler that reduce register usage while avoiding	Evan Cheng
2010-04-07	Three changes:	Chris Lattner
2010-02-09	move target-independent opcodes out of TargetInstrInfo	Chris Lattner
2010-02-05	When the scheduler unfold a load folding instruction it move some of the pred...	Evan Cheng
2010-01-23	Remove the '-disable-scheduling' flag and replace it with the 'source' option of	Bill Wendling
2010-01-06	The previous code could potentially cause a cycle. Allow ordering w.r.t. a 0 ...	Bill Wendling
2010-01-06	Only check the ordering if there is an ordering for each nodes.	Bill Wendling
2010-01-05	Add a semi-primitive form of scheduling via the "SDNode ordering" to the	Bill Wendling
2010-01-05	Change errs() to dbgs().	David Greene