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path: root/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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2009-01-16new nodes should be added to the worklist, not old nodes.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62359 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-15Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman
and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-03Fix a DAGCombiner abort on an invalid shift count constant. This fixes PR3250.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61613 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-01Fix PR3274: when promoting the condition of a BRCOND node,Duncan Sands
promote from i1 all the way up to the canonical SetCC type. In order to discover an appropriate type to use, pass MVT::Other to getSetCCResultType. In order to be able to do this, change getSetCCResultType to take a type as an argument, not a value (this is also more logical). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61542 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23Change comments so everybody can understand them, hopefully.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61405 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23Add another permutation where we should get rid of a-a.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61401 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-23One more permutation of subtracting off a base value.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61361 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-16A new dag combine; several permutations of thisDale Johannesen
are there under ADD, this one was missing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61107 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-12Redo the arithmetic with overflow architecture. I was changing the semantics ofBill Wendling
ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60915 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-11Clarify FIXME.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60867 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-11Make fix for r60829 less conservative to allow the proper optimization forMon P Wang
vec_extract-sse4.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60865 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-10If ADD, SUB, or MUL have an overflow bit that's used, don't do transformation onBill Wendling
them. The DAG combiner expects that nodes that are transformed have one value result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60857 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-10Fixed a bug when trying to optimize a extract vector element of aMon P Wang
bit convert that changes the number of elements of a shuffle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60829 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-02One more transformation.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60432 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-02Add a few more transformations.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60391 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-27Add a missing case in visitADD.Dale Johannesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60137 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-24If the type legalizer actually legalized anythingDuncan Sands
(this doesn't happen that often, since most code does not use illegal types) then follow it by a DAG combiner run that is allowed to generate illegal operations but not illegal types. I didn't modify the target combiner code to distinguish like this between illegal operations and illegal types, so it will not produce illegal operations as well as not producing illegal types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59960 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-23Rename SetCCResultContents to BooleanContents. InDuncan Sands
practice these booleans are mostly produced by SetCC, however the concept is more general. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59911 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-22- Move conversion of [SU]ADDO from DAG combiner into legalizer.Bill Wendling
- Add "promote integer type" stuff to the legalizer for these nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59847 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-21Default to converting UADDO to the generic form that SADDO is converted to.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59801 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-21Remove chains. Unnecessary.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59783 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-21Rename "ADDO" to "SADDO" and "UADDO". The "UADDO" isn't equivalent to "ADDC"Bill Wendling
because the boolean it returns to indicate an overflow may not be treated like as a flag. It could be stored to memory, for instance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59780 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-21Implement the sadd_with_overflow intrinsic. This is converted intoBill Wendling
"ISD::ADDO". ISD::ADDO is lowered into a target-independent form that does the addition and then checks if the result is less than one of the operands. (If it is, then there was an overflow.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59779 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-11Fix for PR3040:Bill Wendling
The CC was changed, but wasn't checked to see if it was legal if the DAG combiner was being run after legalization. Threw in a couple of checks just to make sure that it's okay. As far as the PR is concerned, no back-end target actually exhibited this problem, so there isn't an associated testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59035 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-10Added support for the following definition of shufflevector Mon P Wang
<result> = shufflevector <n x <ty>> <v1>, <n x <ty>> <v2>, <m x i32> <mask> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58964 91177308-0d34-0410-b5e6-96231b3b80d8
2008-11-05Type of shuffle mask has changed.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58751 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-28Don't produce invalid comparisons after legalize.Chris Lattner
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58320 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-19Use a legal integer type for vector shuffle maskDuncan Sands
elements. Otherwise LegalizeTypes will, reasonably enough, legalize the mask, which may result in it no longer being a BUILD_VECTOR node (LegalizeDAG simply ignores the legality or not of vector masks). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57782 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-18Teach DAGCombine to fold constant offsets into GlobalAddress nodes,Dan Gohman
and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-17Define patterns for shld and shrd that match immediateDan Gohman
shift counts, and patterns that match dynamic shift counts when the subtract is obscured by a truncate node. Add DAGCombiner support for recognizing rotate patterns when the shift counts are defined by truncate nodes. Fix and simplify the code for commuting shld and shrd instructions to work even when the given instruction doesn't have a parent, and when the caller needs a new instruction. These changes allow LLVM to use the shld, shrd, rol, and ror instructions on x86 to replace equivalent code using two shifts and an or in many more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57662 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-14Rename LoadX to LoadExt.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57526 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-09Rename APFloat::convertToAPInt to bitcastToAPInt toDale Johannesen
make it clearer what the function does. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57325 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-26Rename ConstantSDNode's getSignExtended to getSExtValue, forDan Gohman
consistancy with ConstantInt, and re-implement it in terms of ConstantInt's getSExtValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56700 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24Reapplying r56550Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56553 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24Temporarily revert r56550 until missing commit can be added.Eric Christopher
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56551 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-24Refactor the constant folding code into it's own function. And call it from bothBill Wendling
the SelectionDAG and DAGCombiner code. The only functionality change is that now the DAG combiner is performing the constant folding for these operations instead of being a no-op. This is *not* in response to a bug, so there isn't a testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56550 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-22Per review feedback: Only performEvan Cheng
(srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) etc. when both "trunc" and "and" have single uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56452 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-12Change ConstantSDNode and ConstantFPSDNode to use ConstantInt* andDan Gohman
ConstantFP* instead of APInt and APFloat directly. This reduces the amount of time to create ConstantSDNode and ConstantFPSDNode nodes when ConstantInt* and ConstantFP* respectively are already available, as is the case in SelectionDAGBuild.cpp. Also, it reduces the amount of time to legalize constants into constant pools, and the amount of time to add ConstantFP operands to MachineInstrs, due to eliminating ConstantInt::get and ConstantFP::get calls. It increases the amount of work needed to create new constants in cases where the client doesn't already have a ConstantInt* or ConstantFP*, such as legalize expanding 64-bit integer constants to 32-bit constants. And it adds a layer of indirection for the accessor methods. But these appear to be outweight by the benefits in most cases. It will also make it easier to make ConstantSDNode and ConstantFPNode more consistent with ConstantInt and ConstantFP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56162 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-12Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman
with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-08In visitUREM, arrange for the temporary UDIV node to beDan Gohman
revisited, consistent with the code in visitSREM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55923 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-08Revert my previous change -- the subtraction of two constants was a no-opBill Wendling
before. This is taken care of in the selection DAG pass. In my opinion, this should be in one place or the other. I.e., it should probably be removed from the DAG combiner (along with the other arithmetic transformations on constants that are essentially no-ops). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55889 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-07ConvertBill Wendling
// fold (sub c1, c2) -> c1-c2 from a no-op into an actual transformation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55886 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-05Fix a search+replace-o.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55824 91177308-0d34-0410-b5e6-96231b3b80d8
2008-09-04Clean up uses of TargetLowering::getTargetMachine.Dan Gohman
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55769 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31Another situation where ROTR is cheaper than ROTL.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55577 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31For this pattern, ROTR is the cheaper option.Bill Wendling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55576 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-31- Fix comment so that it describes how the code really works:Bill Wendling
// fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> // (rotl x, y) // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> // (rotr x, (sub 32, y)) Example: (x == 0xDEADBEEF and y == 4) (x << 4) | (x >> 28) => 0xEADBEEF0 | 0x0000000D => 0xEADBEEFD (rotl x, 4) => 0xEADBEEFD (rotr x, 28) => 0xEADBEEFD - Fix comment and code for second version. It wasn't using the rot* propertly. // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> // (rotr x, y) // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> // (rotl x, (sub 32, y)) (x << 28) | (x >> 4) => 0xD0000000 | 0x0DEADBEE => 0xDDEADBEE (rotl x, 4) => 0xEADBEEFD (rotr x, 28) => (0xEADBEEFD) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55575 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30fix some 80-col violationsGabor Greif
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55571 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-30Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 ↵Evan Cheng
shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55558 91177308-0d34-0410-b5e6-96231b3b80d8
2008-08-29Fix 80 col. violations.Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55551 91177308-0d34-0410-b5e6-96231b3b80d8
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