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path: root/lib/CodeGen/ScheduleDAGInstrs.h
AgeCommit message (Expand)Author
2012-03-07misched prep: Expose the ScheduleDAGInstrs interface so targets mayAndrew Trick
2012-03-07misched prep: Remove LLVM_LIBRARY_VISIBILITY from ScheduleDAGInstrs.Andrew Trick
2012-03-07misched prep: Comment the ScheduleDAGInstrs interface.Andrew Trick
2012-03-07misched prep: Cleanup ScheduleDAGInstrs interface.Andrew Trick
2012-03-07misched prep: remove extra "protected"Andrew Trick
2012-03-07misched prep: rename InsertPos to End.Andrew Trick
2012-03-07misched preparation: rename core scheduler methods for consistency.Andrew Trick
2012-03-07commentAndrew Trick
2012-03-07misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick
2012-03-07ScheduleDAGInstrs commentsAndrew Trick
2012-03-07misched preparation: modularize schedule emission.Andrew Trick
2012-03-07Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick
2012-03-07Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ...Andrew Trick
2012-03-07misched commentsAndrew Trick
2012-02-24ScheduleDAGInstrs.h:155: warning: suggest parentheses around `&&' within `||'.Nick Lewycky
2012-02-24PostRA sched: speed up physreg tracking by not abusing SparseSet.Andrew Trick
2012-02-23PostRASched: Convert physreg def/use tracking to Jakob's SparseSet.Andrew Trick
2012-02-22misched: Use SparseSet for VRegDegs for constant time clear().Andrew Trick
2012-02-22Initialize SUnits before DAG building.Andrew Trick
2012-01-14misched: Initial code for building an MI level scheduling DAGAndrew Trick
2012-01-14Move physreg dependency generation into aptly named addPhysRegDeps.Andrew Trick
2012-01-14misched: Added ScheduleDAGInstrs::IsPostRAAndrew Trick
2012-01-07Added a late machine instruction copy propagation pass. This catchesEvan Cheng
2011-10-07PostRA scheduler fix. Clear stale loop dependencies.Andrew Trick
2011-10-07whitespaceAndrew Trick
2011-06-02Update DBG_VALUEs while breaking anti dependencies.Devang Patel
2011-06-02During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALU...Devang Patel
2010-10-23Properly model the latency of register defs which are 1) function returns orEvan Cheng
2010-09-10Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng
2010-07-24Change ScheduleDAGInstrs::Defs and ::Uses to be variable-size vectorsBob Wilson
2010-06-29When processing loops for scheduling latencies (used for live outs on loopJim Grosbach
2010-05-11I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename itDuncan Sands
2010-05-01Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman
2010-03-10Progress towards shepherding debug info through SelectionDAG.Dale Johannesen
2009-10-18Spill slots cannot alias.Evan Cheng
2009-10-12Remove a redundant member variable.Dan Gohman
2009-10-09Factor out LiveIntervalAnalysis' code to determine whether an instructionDan Gohman
2009-09-18Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ...Evan Cheng
2009-08-19Use the schedule itinerary operand use/def cycle information to adjust depend...David Goodwin
2009-02-11When scheduling a block in parts, keep track of the overallDan Gohman
2009-02-10Factor out more code for computing register live-range informationforDan Gohman
2009-02-06Move ScheduleDAGInstrs.h to be a private header. Front-endsDan Gohman
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