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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10728 91177308-0d34-0410-b5e6-96231b3b80d8
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info (since multiple reg types may share the same reg class).
(2) Remove machine-specific regalloc. methods that are no longer needed.
In particular, arguments and return value from a call do not need
machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
overloading when an include file is omitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7329 91177308-0d34-0410-b5e6-96231b3b80d8
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a vector. This makes asserting on array bounds easier.
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* Reduce number of #includes, sometimes drastically (LiveRangeInfo.h lost _7_)
* Move instrIsFeasible() from InstrScheduling.h to SchedPriorities.h
* Delete blank lines at end of files
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@992 91177308-0d34-0410-b5e6-96231b3b80d8
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assembly output
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@603 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@587 91177308-0d34-0410-b5e6-96231b3b80d8
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* Machine.h
* InstInfo.h
* SchedInfo.h
TODO: Split out reg info stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@567 91177308-0d34-0410-b5e6-96231b3b80d8
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Move files from lib/CodeGen/TargetMachine to lib/Target
Move TargetData.h and TargetMachine.h to Target/{Data.h|Machine.h}
Prepare to split TargetMachine.h into several smaller files
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@566 91177308-0d34-0410-b5e6-96231b3b80d8
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--Ruchira
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