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2013-04-05Buildbot fix for r178851: mistake was in wrong ↵Stepan Dyatkovskiy
TargetRegisterInfo::getRegClass usage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178854 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Add obj2yaml to test dependenciesAlexey Samsonov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178852 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Fix for PR14824: "Optimization arm_ldst_opt inserts newly generated ↵Stepan Dyatkovskiy
instruction vldmia at incorrect position". Patch introduces memory operands tracking in ARMLoadStoreOpt::LoadStoreMultipleOpti. For each register it keeps the order of load operations as it was before optimization pass. It is kind of deep improvement of fix proposed by Hao: http://llvm.org/bugs/show_bug.cgi?id=14824#c4 But it also tracks conflicts between different register classes (e.g. D2 and S5). For more details see: Bug description: http://llvm.org/bugs/show_bug.cgi?id=14824 LLVM Commits discussion: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130311/167936.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130318/168688.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130325/169376.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130401/170238.html git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178851 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Add a SchedMachineModel for the PPC G5Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178850 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05The ppc bots say this is the last broken line, so lets try one more :-(Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178849 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Add a SchedMachineModel for the PPC A2Hal Finkel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178848 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05One more try before I just delete the macho bits until tomorrow.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Fix bug in PEI's virtual-register scavengingHal Finkel
This change fixes a bug that I introduced in r178058. After a register is scavenged using one of the available spills slots the instruction defining the virtual register needs to be moved to after the spill code. The scavenger has already processed the defining instruction so that registers killed by that instruction are available for definition in that same instruction. Unfortunately, after this, the scavenger needs to iterate through the spill code and then visit, again, the instruction that defines the now-scavenged register. In order to avoid confusion, the register scavenger needs the ability to 'back up' through the spill code so that it can again process the instructions in the appropriate order. Prior to this fix, once the scavenger reached the just-moved instruction, it would assert if it killed any registers because, having already processed the instruction, it believed they were undefined. Unfortunately, I don't yet have a small test case. Thanks to Pranav Bhandarkar for diagnosing the problem and testing this fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178845 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05ARM scheduler model: Add scheduler info to more instructions and resourceArnold Schwaighofer
descriptions for compares git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178844 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05More test loosening.Rafael Espindola
Sorry for so many commits, but llvm is still building on my ppc vm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178843 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05ARM scheduler model: Swift has varying latencies, uops for simple ALU opsArnold Schwaighofer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178842 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Loosen this test too.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178841 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Loosen this test.Rafael Espindola
Looks like there is a big endian/little endian problem here. Loosen the test to try to get the bots green while llvm builds on a ppc qemu vm. The failure was in http://lab.llvm.org:8011/builders/clang-ppc64-elf-linux2/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178839 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Remove empty directory.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178837 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Move obj2yaml to tools to sort out make's dependencies.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178835 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Build obj2yaml with configure+make.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178833 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Add a test for obj2yaml in preparation for refactoring it.Rafael Espindola
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Clean up some confusing language, and use more realistic examples.Jakob Stoklund Olesen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178828 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05RegisterPressure heuristics currently require signed comparisons.Andrew Trick
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178823 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05Disable DFSResult for ConvergingScheduler.Andrew Trick
For now, just save the compile time since the ConvergingScheduler heuristics don't use this analysis. We'll probably enable it later after compile-time investigation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178822 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05MachineScheduler: format DEBUG output.Andrew Trick
I'm getting more serious about tuning and enabling on x86/ARM. Start by making the trace readable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178821 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04LoopVectorizer: Pass OperandValueKind information to the cost modelArnold Schwaighofer
Pass down the fact that an operand is going to be a vector of constants. This should bring the performance of MultiSource/Benchmarks/PAQ8p/paq8p on x86 back. It had degraded to scalar performance due to my pervious shift cost change that made all shifts expensive on x86. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178809 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04X86 cost model: Differentiate cost for vector shifts of constantsArnold Schwaighofer
SSE2 has efficient support for shifts by a scalar. My previous change of making shifts expensive did not take this into account marking all shifts as expensive. This would prevent vectorization from happening where it is actually beneficial. With this change we differentiate between shifts of constants and other shifts. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178808 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04CostModel: Add parameter to instruction cost to further classify operand valuesArnold Schwaighofer
On certain architectures we can support efficient vectorized version of instructions if the operand value is uniform (splat) or a constant scalar. An example of this is a vector shift on x86. We can efficiently support for (i = 0 ; i < ; i += 4) w[0:3] = v[0:3] << <2, 2, 2, 2> but not for (i = 0; i < ; i += 4) w[0:3] = v[0:3] << x[0:3] This patch adds a parameter to getArithmeticInstrCost to further qualify operand values as uniform or uniform constant. Targets can then choose to return a different cost for instructions with such operand values. A follow-up commit will test this feature on x86. radar://13576547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Debug Info: revert 178722 for now.Manman Ren
There is a difference for FORM_ref_addr between DWARF 2 and DWARF 3+. Since Eric is against guarding DWARF 2 ref_addr with DarwinGDBCompat, we are still in discussion on how to handle this. The correct solution is to update our header to say version 4 instead of version 2 and update tool chains as well. rdar://problem/13559431 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178806 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04typoAdrian Prantl
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Rename the current PPC BCL definition to BCLalwaysHal Finkel
BCL is normally a conditional branch-and-link instruction, but has an unconditional form (which is used in the SjLj code, for example). To make clear that this BCL instruction definition is specifically the special unconditional form (which does not meaningfully take a condition-register input), rename it to BCLalways. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178803 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04PPC: Improve code generation for mixed-precision reciprocal sqrtHal Finkel
The DAGCombine logic that recognized a/sqrt(b) and transformed it into a multiplication by the reciprocal sqrt did not handle cases where the sqrt and the division were separated by an fpext or fptrunc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178801 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Hexagon: Expand br_cc.Jyotsna Verma
It fixes following tests for Hexagon: CodeGen/Generic/2003-07-29-BadConstSbyte.ll CodeGen/Generic/2005-10-21-longlonggtu.ll CodeGen/Generic/2009-04-28-i128-cmp-crash.ll CodeGen/Generic/MachineBranchProb.ll CodeGen/Generic/builtin-expect.ll CodeGen/Generic/pr12507.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178794 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Reassociate: Avoid iterator invalidation.Benjamin Kramer
OpndPtrs stored pointers into the Opnd vector that became invalid when the vector grows. Store indices instead. Sadly I only have a large testcase that only triggers under valgrind, so I didn't include it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178793 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Disable 2010-10-01-crash.ll for Hexagon as the Hexagon frontend willJyotsna Verma
never produce a byval parameter with size < 8 bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178792 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Add back parsing of header charactestics.Rafael Espindola
It had been dropped during the switch to yaml::IO. Also add a test going from yaml2obj to llvm-readobj. It can be extended as we add more fields/formats to yaml2obj. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178786 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04[XCore] Add bru instruction.Richard Osborne
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04[XCore] The RRegs register class is a superset of GRRegs.Richard Osborne
At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Missing wordEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Avoid high-latency false CPSR dependencies even for tMOVSi.Jakob Stoklund Olesen
The Thumb2SizeReduction pass avoids false CPSR dependencies, except it still aggressively creates tMOVi8 instructions because they are so common. Avoid creating false CPSR dependencies even for tMOVi8 instructions when the the CPSR flags are known to have high latency. This allows integer computation to overlap floating point computations. Also process blocks in a reverse post-order and propagate high-latency flags to successors. <rdar://problem/13468102> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178773 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04FormattingEli Bendersky
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178771 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Revert r178713Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178769 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04New-password-test commit.Stepan Dyatkovskiy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178765 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04R600: Use a mask for offsets when encoding instructionsVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178763 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04R600: Fix wrong address when substituting ENDIFVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178762 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04R600: Take export into account when computing cf addressVincent Lejeune
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178761 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Propagate path to ASan/MSan symbolizer into test environment to produce ↵Alexey Samsonov
useful reports on errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178749 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Document the return value of SmallSet insert.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178742 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Add SPARC v9 support for select on 64-bit compares.Jakob Stoklund Olesen
This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178737 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Explicitly add -Wl,--export-all-symbols on mingw/cygwin.Rafael Espindola
Looks like cmake on windows is not expanding ENABLE_EXPORTS to -Wl,--export-all-symbols on mingw or cygwin, so add this back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178730 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Don't export symbols in every binary on linux.Rafael Espindola
On freebsd this makes sure that symbols are exported on the binaries that need them. The net result is that we should get symbols in the binaries that need them on every platform. On linux x86-64 this reduces the size of the bin directory from 262MB to 250MB. Patch by Stephen Checkoway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178725 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-04Debug Info: according to DWARF 2, FORM_ref_addr the same size as an address onManman Ren
the target system. It was hard-coded to 4 bytes before. I can't get llvm to generate a ref_addr on a reasonably sized testing case. rdar://problem/13559431 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178722 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Refactored out the helper method FindPredecessorAutoreleaseWithSafePath from ↵Michael Gottesman
ObjCARCOpt::OptimizeReturns. Now ObjCARCOpt::OptimizeReturns is easy to read and reason about. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178715 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-03Refactored out the helper function FindPredecessorRetainWithSafePath from ↵Michael Gottesman
ObjCARCOpt::OptimizeReturns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178714 91177308-0d34-0410-b5e6-96231b3b80d8
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