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| author | Richard Osborne <richard@xmos.com> | 2013-04-04 20:05:35 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-04-04 20:05:35 +0000 |
| commit | e50faa754b946d5240c1d4e84e64b7e84d4e27b1 (patch) | |
| tree | 76f0faaefe34dcb0a44e37844f1fc324a885f374 | |
| parent | c6ff29713d69b4a41c225cbde9c82e4a350dbfac (diff) | |
[XCore] Add bru instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.td | 3 | ||||
| -rw-r--r-- | test/MC/Disassembler/XCore/xcore.txt | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 472bff11b2..03653cb2b3 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -924,6 +924,9 @@ def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i), "bru $i\n$t", [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>; +let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in +def BRU_1r : _F1R<0b001010, (outs), (ins GRRegs:$a), "bru $a", []>; + let Defs=[SP], neverHasSideEffects=1 in def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>; diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt index 930bd0338d..99e54e9857 100644 --- a/test/MC/Disassembler/XCore/xcore.txt +++ b/test/MC/Disassembler/XCore/xcore.txt @@ -95,6 +95,9 @@ # CHECK: bla r6 0xe6 0x27 +# CHECK: bru r8 +0xe8 0x2f + # CHECK: syncr res[r7] 0xf7 0x87 |