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2012-07-17This is another case where instcombine demanded bits optimization createdEvan Cheng
large immediates. Add dag combine logic to recover in case the large immediates doesn't fit in cmp immediate operand field. int foo(unsigned long l) { return (l>> 47) == 1; } we produce %shr.mask = and i64 %l, -140737488355328 %cmp = icmp eq i64 %shr.mask, 140737488355328 %conv = zext i1 %cmp to i32 ret i32 %conv which codegens to movq $0xffff800000000000,%rax andq %rdi,%rax movq $0x0000800000000000,%rcx cmpq %rcx,%rax sete %al movzbl %al,%eax ret TargetLowering::SimplifySetCC would transform (X & -256) == 256 -> (X >> 8) == 1 if the immediate fails the isLegalICmpImmediate() test. For x86, that's immediates which are not a signed 32-bit immediate. Based on a patch by Eli Friedman. PR10328 rdar://9758774 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Reapply r160340. LSR: Limit CollectSubexprs.Andrew Trick
Speculatively fix crashes by code inspection. Can't reproduce them yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160344 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17Revert "LSR: try not to blow up solving combinatorial problems brute force."Andrew Trick
Some units tests crashed on a different platform. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160341 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17LSR: try not to blow up solving combinatorial problems brute force.Andrew Trick
This places limits on CollectSubexprs to constrains the number of reassociation possibilities. It limits the recursion depth and skips over chains of nested recurrences outside the current loop. Fixes PR13361. Although underlying SCEV behavior is still potentially bad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17TableGen: Allow conditional instruction pattern in multiclass.Jim Grosbach
Define a 'null_frag' SDPatternOperator node, which if referenced in an instruction Pattern, results in the pattern being collapsed to be as-if '[]' had been specified instead. This allows supporting a multiclass definition where some instaniations have ISel patterns associated and others do not. For example, multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> { def _x : myI<(outs rc:), (ins rc:), []>; def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>; } defm foo : myMulti<GRa, not>; defm bar : myMulti<GRb>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160333 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Fix function select_cc_f32 in test/CodeGen/Mips/selectcc.ll.Akira Hatanaka
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160329 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Defer checking for registers in the MC AsmMatcher until the after ↵Owen Anderson
user-defined match classes have been checked. This allows the creation of MatchClass's that are supersets of a register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160327 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16fix PR13339 (remove the predecessor from the unwind BB when removing an invoke)Nuno Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160325 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16teach ConstantRange that zero times X is always zeroNuno Lopes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160317 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16For something likeEvan Cheng
uint32_t hi(uint64_t res) { uint_32t hi = res >> 32; return !hi; } llvm IR looks like this: define i32 @hi(i64 %res) nounwind uwtable ssp { entry: %lnot = icmp ult i64 %res, 4294967296 %lnot.ext = zext i1 %lnot to i32 ret i32 %lnot.ext } The optimizer has optimize away the right shift and truncate but the resulting constant is too large to fit in the 32-bit immediate field. The resulting x86 code is worse as a result: movabsq $4294967296, %rax ## imm = 0x100000000 cmpq %rax, %rdi sbbl %eax, %eax andl $1, %eax This patch teaches the x86 lowering code to handle ult against a large immediate with trailing zeros. It will issue a right shift and a truncate followed by a comparison against a shifted immediate. shrq $32, %rdi testl %edi, %edi sete %al movzbl %al, %eax It also handles a ugt comparison against a large immediate with trailing bits set. i.e. X > 0x0ffffffff -> (X >> 32) >= 1 rdar://11866926 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Minor cleanup and docs.Nadav Rotem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160311 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16MIPS: Create two definitions for __builtin_mips_shll_qb builtin.Simon Atanasyan
The first variant accepts immediate number as the second argument. The second variant accepts register operand as the second argument. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160307 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Make ComputeDemandedBits return a deterministic result when computing an ↵Nadav Rotem
AssertZext value. In the added testcase the constant 55 was behind an AssertZext of type i1, and ComputeDemandedBits reported that some of the bits were both known to be one and known to be zero. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160305 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard
This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "include/llvm: Add R600 Intrinsics v6"Tom Stellard
This reverts commit 600f7a90f3eef4c5108179b43e27cfd9e5de7cdc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "Build script changes for R600/SI Codegen v6"Tom Stellard
This reverts commit e3013202259ed1e006c21817c63cf25d75982721. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "test/CodeGen/R600: Add some basic tests v6"Tom Stellard
This reverts commit 11d3457afcda7848448dd7f11b2ede6552ffb9ea. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160300 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, ↵Tom Stellard
<llvm/IRBuilder.h> and <llvm/TypeBuilder.h>" This reverts commit 0258a6bdd30802f5cc0e8e57c8e768fde2aef590. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add ↵Tom Stellard
AMDGPUCommonTableGen." This reverts commit ebc934ba32ee71abbb8f0f2eb6a0fbaa613ba0d2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160298 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as ↵Tom Stellard
conditional operator..." This reverts commit 29f28bc14ad5a907f5dc849f004fafeec0aab33a. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160297 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in ↵Tom Stellard
nonreturn function, instead of assert(0)." This reverts commit 4ba4acc1bc2561b944a571edbb6a2dc78e357dfe. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160296 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert "Target/AMDGPU: Fix includes, or msvc build failed."Tom Stellard
This reverts commit fef4aa1b16fcf7a472559abbbcf4c1adc9eb5ca6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160295 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16make ConstantRange::getSetSize() properly compute the size of wrapped and ↵Nuno Lopes
full sets. Make it always return APInts with the same bitwidth for the same ConstantRange bitwidth to simply clients git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160294 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16With r160248 in place this code is no longer needed.Chad Rosier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16[asan] a bit more refactoring, addressed some of the style comments from ↵Kostya Serebryany
chandlerc, partially implemented crash callback merging (under flag) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160290 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16MSVC's implementation of isalnum will assert on characters > 255, so we need ↵Aaron Ballman
to use an unsigned char to ensure the integer promotion happens properly. This fixes an assert in debug builds with CodeGen\X86\utf8.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160286 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16[asan] refactor instrumentation to allow merging the crash callbacks (not ↵Kostya Serebryany
fully implemented yet, no functionality change except the BB order) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160284 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Target/AMDGPU: Fix includes, or msvc build failed.NAKAMURA Takumi
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160280 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn ↵NAKAMURA Takumi
function, instead of assert(0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160279 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional ↵NAKAMURA Takumi
operator... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160278 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Doubleword Shift Left Logical Plus 32Jack Carter
Mips shift instructions DSLL, DSRL and DSRA are transformed into DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between 32 and 63 Here is a description of DSLL: Purpose: Doubleword Shift Left Logical Plus 32 To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits Description: GPR[rd] <- GPR[rt] << (sa+32) The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the emptied bits; the result is placed in GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa. This patch implements the direct object output of these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add ↵NAKAMURA Takumi
AMDGPUCommonTableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160276 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> ↵NAKAMURA Takumi
and <llvm/TypeBuilder.h> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160275 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Fix tests that failed on i686-win32 after r160248:Alexey Samsonov
1. FileCheck-ize epilogue.ll and allow another asm instruction to restore %rsp. 2. Remove check in widen_arith-3.ll that was hitting instruction in epilogue instead of vector add. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16test/CodeGen/R600: Add some basic tests v6Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160273 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Build script changes for R600/SI Codegen v6Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160272 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16include/llvm: Add R600 Intrinsics v6Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160271 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16[asan] initialize asan error callbacks in runOnModule instead of doing that ↵Kostya Serebryany
on-demand git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160269 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Fix a bug in the 3-address conversion of LEA when one of the operands is anNadav Rotem
undef virtual register. The problem is that ProcessImplicitDefs removes the definition of the register and marks all uses as undef. If we lose the undef marker then we get a register which has no def, is not marked as undef. The live interval analysis does not collect information for these virtual registers and we crash in later passes. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160260 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Revert r160254 temporarily.Chandler Carruth
It turns out that ASan relied on the at-the-end block insertion order to (purely by happenstance) disable some LLVM optimizations, which in turn start firing when the ordering is made more "normal". These optimizations in turn merge many of the instrumentation reporting calls which breaks the return address based error reporting in ASan. We're looking at several different options for fixing this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Teach AddressSanitizer to create basic blocks in a more natural order.Chandler Carruth
This is particularly useful to the backend code generators which try to process things in the incoming function order. Also, cleanup some uses of IRBuilder to be a bit simpler and more clear. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160254 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Add a basic test for AddressSanitizer. This is just a bare-bonesChandler Carruth
functionality test. In general, unless the functionality is substantially separated, we should lump more basic testing into this file. The test running infrastructure likes having a few test files with more comprehensive testing within them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160253 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Add support for attaching branch weight metadata directly from the IRBuilder.Chandler Carruth
Added a basic unit test for this with CreateCondBr. I didn't go all the way and test the switch side as the boilerplate for setting up the switch IRBuilder unit tests is a lot more. Fortunately, the two share all the interesting code paths. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Add a boring bit of boilerplate to start testing IRBuilder::CreateCondBr.Chandler Carruth
This is in anticipation of changing CreateCondBr and wanting to test those changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16Move the IRBuilder unittest from Support to VMCore. This got missed inChandler Carruth
the original move of IRBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160249 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16This CL changes the function prologue and epilogue emitted on X86 when stack ↵Alexey Samsonov
needs realignment. It is intended to fix PR11468. Old prologue and epilogue looked like this: push %rbp mov %rsp, %rbp and $alignment, %rsp push %r14 push %r15 ... pop %r15 pop %r14 mov %rbp, %rsp pop %rbp The problem was to reference the locations of callee-saved registers in exception handling: locations of callee-saved had to be re-calculated regarding the stack alignment operation. It would take some effort to implement this in LLVM, as currently MachineLocation can only have the form "Register + Offset". Funciton prologue and epilogue are now changed to: push %rbp mov %rsp, %rbp push %14 push %15 and $alignment, %rsp ... lea -$size_of_saved_registers(%rbp), %rsp pop %r15 pop %r14 pop %rbp Reviewed by Chad Rosier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160248 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Move llvm/Support/TypeBuilder.h -> llvm/TypeBuilder.h. This completesChandler Carruth
the move of *Builder classes into the Core library. No uses of this builder in Clang or DragonEgg I could find. If there is a desire to have an IR-building-support library that contains all of these builders, that can be easily added, but currently it seems likely that these add no real overhead to VMCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160243 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Update the header guard I missed when moving the header.Chandler Carruth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160242 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-15Move llvm/Support/MDBuilder.h to llvm/MDBuilder.h, to live withChandler Carruth
IRBuilder, DIBuilder, etc. This is the proper layering as MDBuilder can't be used (or implemented) without the Core Metadata representation. Patches to Clang and Dragonegg coming up. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160237 91177308-0d34-0410-b5e6-96231b3b80d8
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