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basic blocks.
- Calling getUser in a loop is much more expensive than iterating over a few instructions.
- Use it instead of the open-coded loop in AddrModeMatcher.
- 5% speedup on ARMDisassembler.cpp Release builds.
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instructions.
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change.
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not get there any other way.
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Maybe some targets should use this as well.
Patch by Evgeniy Stepanov!
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AnalyzeBranch doesn't change the successor, just the order.
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-3% on ARMDissasembler.cpp.
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just to remove no blocks from the maps.
-15% on ARMDisassembler.cpp (Release build). It's not that great to add another
layer of caching to the caching-heavy LVI but I don't see a better way.
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libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit. This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit. This should result in lesser calls to __morestack.
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Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp. This isn't correct since __morestack expects the call
to be followed directly by a ret.
This commit also adjusts the relevant test-case.
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the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.
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rdar://10510150
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causing the optimisation to occur
Turns out long long + unsigned long long is unsigned. Doh!
Fixes http://llvm.org/bugs/show_bug.cgi?id=11455
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rdar://10514247
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change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
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Its meaning was slightly mysterious without looking at
subclasses.
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Makes failures more self-explanatory.
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argument value type. Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467
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Add the 16-bit lane variants while I'm at it.
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function of the callee once and not for every invoke in the caller.
The callee is usually smaller than the caller, too. This reduces the compile
time of ARMDisassembler.cpp by 32% (Release build). It still takes ages to
compile though.
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assumptions
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point vectors. Also add the test case for 256-bit integer vectors.
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haz. rec.
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instruction in Sequence is a Noop
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Add FIXMEs to places that are non-trivial to fix.
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The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.
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for the suggestion, Eric.
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TLI isn't being passed to ensure we don't miss opportunities to fold calls.
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rdar://10500969
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Oops, missed another missing file from r145629.
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Missing file from r145629.
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