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-rw-r--r--test/MC/Disassembler/AArch64/gicv3-regs.txt222
-rw-r--r--test/MC/Disassembler/ARM/thumb2.txt5
-rw-r--r--test/MC/Disassembler/X86/simple-tests.txt15
3 files changed, 242 insertions, 0 deletions
diff --git a/test/MC/Disassembler/AArch64/gicv3-regs.txt b/test/MC/Disassembler/AArch64/gicv3-regs.txt
new file mode 100644
index 0000000000..4351f6460c
--- /dev/null
+++ b/test/MC/Disassembler/AArch64/gicv3-regs.txt
@@ -0,0 +1,222 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s | FileCheck %s
+
+0x8 0xcc 0x38 0xd5
+# CHECK: mrs x8, icc_iar1_el1
+0x1a 0xc8 0x38 0xd5
+# CHECK: mrs x26, icc_iar0_el1
+0x42 0xcc 0x38 0xd5
+# CHECK: mrs x2, icc_hppir1_el1
+0x51 0xc8 0x38 0xd5
+# CHECK: mrs x17, icc_hppir0_el1
+0x7d 0xcb 0x38 0xd5
+# CHECK: mrs x29, icc_rpr_el1
+0x24 0xcb 0x3c 0xd5
+# CHECK: mrs x4, ich_vtr_el2
+0x78 0xcb 0x3c 0xd5
+# CHECK: mrs x24, ich_eisr_el2
+0xa9 0xcb 0x3c 0xd5
+# CHECK: mrs x9, ich_elsr_el2
+0x78 0xcc 0x38 0xd5
+# CHECK: mrs x24, icc_bpr1_el1
+0x6e 0xc8 0x38 0xd5
+# CHECK: mrs x14, icc_bpr0_el1
+0x13 0x46 0x38 0xd5
+# CHECK: mrs x19, icc_pmr_el1
+0x97 0xcc 0x38 0xd5
+# CHECK: mrs x23, icc_ctlr_el1
+0x94 0xcc 0x3e 0xd5
+# CHECK: mrs x20, icc_ctlr_el3
+0xbc 0xcc 0x38 0xd5
+# CHECK: mrs x28, icc_sre_el1
+0xb9 0xc9 0x3c 0xd5
+# CHECK: mrs x25, icc_sre_el2
+0xa8 0xcc 0x3e 0xd5
+# CHECK: mrs x8, icc_sre_el3
+0xd6 0xcc 0x38 0xd5
+# CHECK: mrs x22, icc_igrpen0_el1
+0xe5 0xcc 0x38 0xd5
+# CHECK: mrs x5, icc_igrpen1_el1
+0xe7 0xcc 0x3e 0xd5
+# CHECK: mrs x7, icc_igrpen1_el3
+0x16 0xcd 0x38 0xd5
+# CHECK: mrs x22, icc_seien_el1
+0x84 0xc8 0x38 0xd5
+# CHECK: mrs x4, icc_ap0r0_el1
+0xab 0xc8 0x38 0xd5
+# CHECK: mrs x11, icc_ap0r1_el1
+0xdb 0xc8 0x38 0xd5
+# CHECK: mrs x27, icc_ap0r2_el1
+0xf5 0xc8 0x38 0xd5
+# CHECK: mrs x21, icc_ap0r3_el1
+0x2 0xc9 0x38 0xd5
+# CHECK: mrs x2, icc_ap1r0_el1
+0x35 0xc9 0x38 0xd5
+# CHECK: mrs x21, icc_ap1r1_el1
+0x4a 0xc9 0x38 0xd5
+# CHECK: mrs x10, icc_ap1r2_el1
+0x7b 0xc9 0x38 0xd5
+# CHECK: mrs x27, icc_ap1r3_el1
+0x14 0xc8 0x3c 0xd5
+# CHECK: mrs x20, ich_ap0r0_el2
+0x35 0xc8 0x3c 0xd5
+# CHECK: mrs x21, ich_ap0r1_el2
+0x45 0xc8 0x3c 0xd5
+# CHECK: mrs x5, ich_ap0r2_el2
+0x64 0xc8 0x3c 0xd5
+# CHECK: mrs x4, ich_ap0r3_el2
+0xf 0xc9 0x3c 0xd5
+# CHECK: mrs x15, ich_ap1r0_el2
+0x2c 0xc9 0x3c 0xd5
+# CHECK: mrs x12, ich_ap1r1_el2
+0x5b 0xc9 0x3c 0xd5
+# CHECK: mrs x27, ich_ap1r2_el2
+0x74 0xc9 0x3c 0xd5
+# CHECK: mrs x20, ich_ap1r3_el2
+0xa 0xcb 0x3c 0xd5
+# CHECK: mrs x10, ich_hcr_el2
+0x5b 0xcb 0x3c 0xd5
+# CHECK: mrs x27, ich_misr_el2
+0xe6 0xcb 0x3c 0xd5
+# CHECK: mrs x6, ich_vmcr_el2
+0x93 0xc9 0x3c 0xd5
+# CHECK: mrs x19, ich_vseir_el2
+0x3 0xcc 0x3c 0xd5
+# CHECK: mrs x3, ich_lr0_el2
+0x21 0xcc 0x3c 0xd5
+# CHECK: mrs x1, ich_lr1_el2
+0x56 0xcc 0x3c 0xd5
+# CHECK: mrs x22, ich_lr2_el2
+0x75 0xcc 0x3c 0xd5
+# CHECK: mrs x21, ich_lr3_el2
+0x86 0xcc 0x3c 0xd5
+# CHECK: mrs x6, ich_lr4_el2
+0xaa 0xcc 0x3c 0xd5
+# CHECK: mrs x10, ich_lr5_el2
+0xcb 0xcc 0x3c 0xd5
+# CHECK: mrs x11, ich_lr6_el2
+0xec 0xcc 0x3c 0xd5
+# CHECK: mrs x12, ich_lr7_el2
+0x0 0xcd 0x3c 0xd5
+# CHECK: mrs x0, ich_lr8_el2
+0x35 0xcd 0x3c 0xd5
+# CHECK: mrs x21, ich_lr9_el2
+0x4d 0xcd 0x3c 0xd5
+# CHECK: mrs x13, ich_lr10_el2
+0x7a 0xcd 0x3c 0xd5
+# CHECK: mrs x26, ich_lr11_el2
+0x81 0xcd 0x3c 0xd5
+# CHECK: mrs x1, ich_lr12_el2
+0xa8 0xcd 0x3c 0xd5
+# CHECK: mrs x8, ich_lr13_el2
+0xc2 0xcd 0x3c 0xd5
+# CHECK: mrs x2, ich_lr14_el2
+0xe8 0xcd 0x3c 0xd5
+# CHECK: mrs x8, ich_lr15_el2
+0x3b 0xcc 0x18 0xd5
+# CHECK: msr icc_eoir1_el1, x27
+0x25 0xc8 0x18 0xd5
+# CHECK: msr icc_eoir0_el1, x5
+0x2d 0xcb 0x18 0xd5
+# CHECK: msr icc_dir_el1, x13
+0xb5 0xcb 0x18 0xd5
+# CHECK: msr icc_sgi1r_el1, x21
+0xd9 0xcb 0x18 0xd5
+# CHECK: msr icc_asgi1r_el1, x25
+0xfc 0xcb 0x18 0xd5
+# CHECK: msr icc_sgi0r_el1, x28
+0x67 0xcc 0x18 0xd5
+# CHECK: msr icc_bpr1_el1, x7
+0x69 0xc8 0x18 0xd5
+# CHECK: msr icc_bpr0_el1, x9
+0x1d 0x46 0x18 0xd5
+# CHECK: msr icc_pmr_el1, x29
+0x98 0xcc 0x18 0xd5
+# CHECK: msr icc_ctlr_el1, x24
+0x80 0xcc 0x1e 0xd5
+# CHECK: msr icc_ctlr_el3, x0
+0xa2 0xcc 0x18 0xd5
+# CHECK: msr icc_sre_el1, x2
+0xa5 0xc9 0x1c 0xd5
+# CHECK: msr icc_sre_el2, x5
+0xaa 0xcc 0x1e 0xd5
+# CHECK: msr icc_sre_el3, x10
+0xd6 0xcc 0x18 0xd5
+# CHECK: msr icc_igrpen0_el1, x22
+0xeb 0xcc 0x18 0xd5
+# CHECK: msr icc_igrpen1_el1, x11
+0xe8 0xcc 0x1e 0xd5
+# CHECK: msr icc_igrpen1_el3, x8
+0x4 0xcd 0x18 0xd5
+# CHECK: msr icc_seien_el1, x4
+0x9b 0xc8 0x18 0xd5
+# CHECK: msr icc_ap0r0_el1, x27
+0xa5 0xc8 0x18 0xd5
+# CHECK: msr icc_ap0r1_el1, x5
+0xd4 0xc8 0x18 0xd5
+# CHECK: msr icc_ap0r2_el1, x20
+0xe0 0xc8 0x18 0xd5
+# CHECK: msr icc_ap0r3_el1, x0
+0x2 0xc9 0x18 0xd5
+# CHECK: msr icc_ap1r0_el1, x2
+0x3d 0xc9 0x18 0xd5
+# CHECK: msr icc_ap1r1_el1, x29
+0x57 0xc9 0x18 0xd5
+# CHECK: msr icc_ap1r2_el1, x23
+0x6b 0xc9 0x18 0xd5
+# CHECK: msr icc_ap1r3_el1, x11
+0x2 0xc8 0x1c 0xd5
+# CHECK: msr ich_ap0r0_el2, x2
+0x3b 0xc8 0x1c 0xd5
+# CHECK: msr ich_ap0r1_el2, x27
+0x47 0xc8 0x1c 0xd5
+# CHECK: msr ich_ap0r2_el2, x7
+0x61 0xc8 0x1c 0xd5
+# CHECK: msr ich_ap0r3_el2, x1
+0x7 0xc9 0x1c 0xd5
+# CHECK: msr ich_ap1r0_el2, x7
+0x2c 0xc9 0x1c 0xd5
+# CHECK: msr ich_ap1r1_el2, x12
+0x4e 0xc9 0x1c 0xd5
+# CHECK: msr ich_ap1r2_el2, x14
+0x6d 0xc9 0x1c 0xd5
+# CHECK: msr ich_ap1r3_el2, x13
+0x1 0xcb 0x1c 0xd5
+# CHECK: msr ich_hcr_el2, x1
+0x4a 0xcb 0x1c 0xd5
+# CHECK: msr ich_misr_el2, x10
+0xf8 0xcb 0x1c 0xd5
+# CHECK: msr ich_vmcr_el2, x24
+0x9d 0xc9 0x1c 0xd5
+# CHECK: msr ich_vseir_el2, x29
+0x1a 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr0_el2, x26
+0x29 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr1_el2, x9
+0x52 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr2_el2, x18
+0x7a 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr3_el2, x26
+0x96 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr4_el2, x22
+0xba 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr5_el2, x26
+0xdb 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr6_el2, x27
+0xe8 0xcc 0x1c 0xd5
+# CHECK: msr ich_lr7_el2, x8
+0x11 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr8_el2, x17
+0x33 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr9_el2, x19
+0x51 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr10_el2, x17
+0x65 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr11_el2, x5
+0x9d 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr12_el2, x29
+0xa2 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr13_el2, x2
+0xcd 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr14_el2, x13
+0xfb 0xcd 0x1c 0xd5
+# CHECK: msr ich_lr15_el2, x27
diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt
index 45dace3b09..31f75b39fa 100644
--- a/test/MC/Disassembler/ARM/thumb2.txt
+++ b/test/MC/Disassembler/ARM/thumb2.txt
@@ -254,9 +254,12 @@
#------------------------------------------------------------------------------
# CHECK: cbnz r7, #6
# CHECK: cbnz r7, #12
+# CHECK: cbz r4, #64
0x1f 0xb9
0x37 0xb9
+0x04 0xb3
+
#------------------------------------------------------------------------------
# CDP/CDP2
@@ -554,6 +557,7 @@
# CHECK: ldr.w r8, [r8, r2, lsl #2]
# CHECK: ldr.w r7, [sp, r2, lsl #1]
# CHECK: ldr.w r7, [sp, r2]
+# CHECK: ldr pc, [sp], #12
# CHECK: ldr r2, [r4, #255]!
# CHECK: ldr r8, [sp, #4]!
# CHECK: ldr lr, [sp, #-4]!
@@ -567,6 +571,7 @@
0x58 0xf8 0x22 0x80
0x5d 0xf8 0x12 0x70
0x5d 0xf8 0x02 0x70
+0x5d 0xf8 0x0c 0xfb
0x54 0xf8 0xff 0x2f
0x5d 0xf8 0x04 0x8f
0x5d 0xf8 0x04 0xed
diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt
index 5ea40eb913..9827a1809f 100644
--- a/test/MC/Disassembler/X86/simple-tests.txt
+++ b/test/MC/Disassembler/X86/simple-tests.txt
@@ -753,3 +753,18 @@
# CHECK: lock
# CHECK-NEXT: xaddq %rcx, %rbx
0xf0 0x48 0x0f 0xc1 0xcb
+
+# rdar://13493622 lldb doesn't print the x86 rep/repne prefix when disassembling
+# CHECK: repne
+# CHECK-NEXT: movsd
+0xf2 0xa5
+# CHECK: repne
+# CHECK-NEXT: movsq
+0xf2 0x48 0xa5
+# CHECK: repne
+# CHECK-NEXT: movb $0, (%rax)
+0xf2 0xc6 0x0 0x0
+# CHECK: rep
+# CHECK-NEXT: lock
+# CHECK-NEXT: incl (%rax)
+0xf3 0xf0 0xff 0x00
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-11-21 16:55:32 +0000